11.1Sjmcneill/* $NetBSD: r7s72100-clock.h,v 1.1.1.5 2019/01/22 14:57:02 jmcneill Exp $ */ 21.1Sjmcneill 31.1.1.5Sjmcneill/* SPDX-License-Identifier: GPL-2.0 41.1.1.5Sjmcneill * 51.1Sjmcneill * Copyright (C) 2014 Renesas Solutions Corp. 61.1Sjmcneill * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 71.1Sjmcneill */ 81.1Sjmcneill 91.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ 101.1Sjmcneill#define __DT_BINDINGS_CLOCK_R7S72100_H__ 111.1Sjmcneill 121.1Sjmcneill#define R7S72100_CLK_PLL 0 131.1.1.4Sjmcneill#define R7S72100_CLK_I 1 141.1.1.4Sjmcneill#define R7S72100_CLK_G 2 151.1Sjmcneill 161.1.1.3Sjmcneill/* MSTP2 */ 171.1.1.3Sjmcneill#define R7S72100_CLK_CORESIGHT 0 181.1.1.3Sjmcneill 191.1Sjmcneill/* MSTP3 */ 201.1.1.3Sjmcneill#define R7S72100_CLK_IEBUS 7 211.1.1.3Sjmcneill#define R7S72100_CLK_IRDA 6 221.1.1.3Sjmcneill#define R7S72100_CLK_LIN0 5 231.1.1.3Sjmcneill#define R7S72100_CLK_LIN1 4 241.1Sjmcneill#define R7S72100_CLK_MTU2 3 251.1.1.3Sjmcneill#define R7S72100_CLK_CAN 2 261.1.1.3Sjmcneill#define R7S72100_CLK_ADCPWR 1 271.1.1.3Sjmcneill#define R7S72100_CLK_PWM 0 281.1Sjmcneill 291.1Sjmcneill/* MSTP4 */ 301.1Sjmcneill#define R7S72100_CLK_SCIF0 7 311.1Sjmcneill#define R7S72100_CLK_SCIF1 6 321.1Sjmcneill#define R7S72100_CLK_SCIF2 5 331.1Sjmcneill#define R7S72100_CLK_SCIF3 4 341.1Sjmcneill#define R7S72100_CLK_SCIF4 3 351.1Sjmcneill#define R7S72100_CLK_SCIF5 2 361.1Sjmcneill#define R7S72100_CLK_SCIF6 1 371.1Sjmcneill#define R7S72100_CLK_SCIF7 0 381.1Sjmcneill 391.1Sjmcneill/* MSTP5 */ 401.1.1.3Sjmcneill#define R7S72100_CLK_SCI0 7 411.1.1.3Sjmcneill#define R7S72100_CLK_SCI1 6 421.1.1.3Sjmcneill#define R7S72100_CLK_SG0 5 431.1.1.3Sjmcneill#define R7S72100_CLK_SG1 4 441.1.1.3Sjmcneill#define R7S72100_CLK_SG2 3 451.1.1.3Sjmcneill#define R7S72100_CLK_SG3 2 461.1Sjmcneill#define R7S72100_CLK_OSTM0 1 471.1Sjmcneill#define R7S72100_CLK_OSTM1 0 481.1Sjmcneill 491.1.1.2Sjmcneill/* MSTP6 */ 501.1.1.3Sjmcneill#define R7S72100_CLK_ADC 7 511.1.1.3Sjmcneill#define R7S72100_CLK_CEU 6 521.1.1.3Sjmcneill#define R7S72100_CLK_DOC0 5 531.1.1.3Sjmcneill#define R7S72100_CLK_DOC1 4 541.1.1.3Sjmcneill#define R7S72100_CLK_DRC0 3 551.1.1.3Sjmcneill#define R7S72100_CLK_DRC1 2 561.1.1.3Sjmcneill#define R7S72100_CLK_JCU 1 571.1.1.2Sjmcneill#define R7S72100_CLK_RTC 0 581.1.1.2Sjmcneill 591.1Sjmcneill/* MSTP7 */ 601.1.1.3Sjmcneill#define R7S72100_CLK_VDEC0 7 611.1.1.3Sjmcneill#define R7S72100_CLK_VDEC1 6 621.1Sjmcneill#define R7S72100_CLK_ETHER 4 631.1.1.3Sjmcneill#define R7S72100_CLK_NAND 3 641.1.1.3Sjmcneill#define R7S72100_CLK_USB0 1 651.1.1.3Sjmcneill#define R7S72100_CLK_USB1 0 661.1Sjmcneill 671.1Sjmcneill/* MSTP8 */ 681.1.1.3Sjmcneill#define R7S72100_CLK_IMR0 7 691.1.1.3Sjmcneill#define R7S72100_CLK_IMR1 6 701.1.1.3Sjmcneill#define R7S72100_CLK_IMRDISP 5 711.1Sjmcneill#define R7S72100_CLK_MMCIF 4 721.1.1.3Sjmcneill#define R7S72100_CLK_MLB 3 731.1.1.3Sjmcneill#define R7S72100_CLK_ETHAVB 2 741.1.1.3Sjmcneill#define R7S72100_CLK_SCUX 1 751.1Sjmcneill 761.1Sjmcneill/* MSTP9 */ 771.1Sjmcneill#define R7S72100_CLK_I2C0 7 781.1Sjmcneill#define R7S72100_CLK_I2C1 6 791.1Sjmcneill#define R7S72100_CLK_I2C2 5 801.1Sjmcneill#define R7S72100_CLK_I2C3 4 811.1.1.3Sjmcneill#define R7S72100_CLK_SPIBSC0 3 821.1.1.3Sjmcneill#define R7S72100_CLK_SPIBSC1 2 831.1.1.3Sjmcneill#define R7S72100_CLK_VDC50 1 /* and LVDS */ 841.1.1.3Sjmcneill#define R7S72100_CLK_VDC51 0 851.1Sjmcneill 861.1Sjmcneill/* MSTP10 */ 871.1Sjmcneill#define R7S72100_CLK_SPI0 7 881.1Sjmcneill#define R7S72100_CLK_SPI1 6 891.1Sjmcneill#define R7S72100_CLK_SPI2 5 901.1Sjmcneill#define R7S72100_CLK_SPI3 4 911.1Sjmcneill#define R7S72100_CLK_SPI4 3 921.1.1.3Sjmcneill#define R7S72100_CLK_CDROM 2 931.1.1.3Sjmcneill#define R7S72100_CLK_SPDIF 1 941.1.1.3Sjmcneill#define R7S72100_CLK_RGPVG2 0 951.1.1.3Sjmcneill 961.1.1.3Sjmcneill/* MSTP11 */ 971.1.1.3Sjmcneill#define R7S72100_CLK_SSI0 5 981.1.1.3Sjmcneill#define R7S72100_CLK_SSI1 4 991.1.1.3Sjmcneill#define R7S72100_CLK_SSI2 3 1001.1.1.3Sjmcneill#define R7S72100_CLK_SSI3 2 1011.1.1.3Sjmcneill#define R7S72100_CLK_SSI4 1 1021.1.1.3Sjmcneill#define R7S72100_CLK_SSI5 0 1031.1Sjmcneill 1041.1Sjmcneill/* MSTP12 */ 1051.1.1.2Sjmcneill#define R7S72100_CLK_SDHI00 3 1061.1.1.2Sjmcneill#define R7S72100_CLK_SDHI01 2 1071.1.1.2Sjmcneill#define R7S72100_CLK_SDHI10 1 1081.1.1.2Sjmcneill#define R7S72100_CLK_SDHI11 0 1091.1Sjmcneill 1101.1.1.3Sjmcneill/* MSTP13 */ 1111.1.1.3Sjmcneill#define R7S72100_CLK_PIX1 2 1121.1.1.3Sjmcneill#define R7S72100_CLK_PIX0 1 1131.1.1.3Sjmcneill 1141.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ 115