r7s72100-clock.h revision 1.1.1.4 
1/*	$NetBSD: r7s72100-clock.h,v 1.1.1.4 2017/11/30 19:40:51 jmcneill Exp $	*/
2
3/*
4 * Copyright (C) 2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 */
11
12#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
13#define __DT_BINDINGS_CLOCK_R7S72100_H__
14
15#define R7S72100_CLK_PLL	0
16#define R7S72100_CLK_I		1
17#define R7S72100_CLK_G		2
18
19/* MSTP2 */
20#define R7S72100_CLK_CORESIGHT	0
21
22/* MSTP3 */
23#define R7S72100_CLK_IEBUS	7
24#define R7S72100_CLK_IRDA	6
25#define R7S72100_CLK_LIN0	5
26#define R7S72100_CLK_LIN1	4
27#define R7S72100_CLK_MTU2	3
28#define R7S72100_CLK_CAN	2
29#define R7S72100_CLK_ADCPWR	1
30#define R7S72100_CLK_PWM	0
31
32/* MSTP4 */
33#define R7S72100_CLK_SCIF0	7
34#define R7S72100_CLK_SCIF1	6
35#define R7S72100_CLK_SCIF2	5
36#define R7S72100_CLK_SCIF3	4
37#define R7S72100_CLK_SCIF4	3
38#define R7S72100_CLK_SCIF5	2
39#define R7S72100_CLK_SCIF6	1
40#define R7S72100_CLK_SCIF7	0
41
42/* MSTP5 */
43#define R7S72100_CLK_SCI0	7
44#define R7S72100_CLK_SCI1	6
45#define R7S72100_CLK_SG0	5
46#define R7S72100_CLK_SG1	4
47#define R7S72100_CLK_SG2	3
48#define R7S72100_CLK_SG3	2
49#define R7S72100_CLK_OSTM0	1
50#define R7S72100_CLK_OSTM1	0
51
52/* MSTP6 */
53#define R7S72100_CLK_ADC	7
54#define R7S72100_CLK_CEU	6
55#define R7S72100_CLK_DOC0	5
56#define R7S72100_CLK_DOC1	4
57#define R7S72100_CLK_DRC0	3
58#define R7S72100_CLK_DRC1	2
59#define R7S72100_CLK_JCU	1
60#define R7S72100_CLK_RTC	0
61
62/* MSTP7 */
63#define R7S72100_CLK_VDEC0	7
64#define R7S72100_CLK_VDEC1	6
65#define R7S72100_CLK_ETHER	4
66#define R7S72100_CLK_NAND	3
67#define R7S72100_CLK_USB0	1
68#define R7S72100_CLK_USB1	0
69
70/* MSTP8 */
71#define R7S72100_CLK_IMR0	7
72#define R7S72100_CLK_IMR1	6
73#define R7S72100_CLK_IMRDISP	5
74#define R7S72100_CLK_MMCIF	4
75#define R7S72100_CLK_MLB	3
76#define R7S72100_CLK_ETHAVB	2
77#define R7S72100_CLK_SCUX	1
78
79/* MSTP9 */
80#define R7S72100_CLK_I2C0	7
81#define R7S72100_CLK_I2C1	6
82#define R7S72100_CLK_I2C2	5
83#define R7S72100_CLK_I2C3	4
84#define R7S72100_CLK_SPIBSC0	3
85#define R7S72100_CLK_SPIBSC1	2
86#define R7S72100_CLK_VDC50	1	/* and LVDS */
87#define R7S72100_CLK_VDC51	0
88
89/* MSTP10 */
90#define R7S72100_CLK_SPI0	7
91#define R7S72100_CLK_SPI1	6
92#define R7S72100_CLK_SPI2	5
93#define R7S72100_CLK_SPI3	4
94#define R7S72100_CLK_SPI4	3
95#define R7S72100_CLK_CDROM	2
96#define R7S72100_CLK_SPDIF	1
97#define R7S72100_CLK_RGPVG2	0
98
99/* MSTP11 */
100#define R7S72100_CLK_SSI0	5
101#define R7S72100_CLK_SSI1	4
102#define R7S72100_CLK_SSI2	3
103#define R7S72100_CLK_SSI3	2
104#define R7S72100_CLK_SSI4	1
105#define R7S72100_CLK_SSI5	0
106
107/* MSTP12 */
108#define R7S72100_CLK_SDHI00	3
109#define R7S72100_CLK_SDHI01	2
110#define R7S72100_CLK_SDHI10	1
111#define R7S72100_CLK_SDHI11	0
112
113/* MSTP13 */
114#define R7S72100_CLK_PIX1	2
115#define R7S72100_CLK_PIX0	1
116
117#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
118