11.1Sjmcneill/* $NetBSD: r8a7740-clock.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-or-later */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright 2014 Ulrich Hecht 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ 91.1Sjmcneill#define __DT_BINDINGS_CLOCK_R8A7740_H__ 101.1Sjmcneill 111.1Sjmcneill/* CPG */ 121.1Sjmcneill#define R8A7740_CLK_SYSTEM 0 131.1Sjmcneill#define R8A7740_CLK_PLLC0 1 141.1Sjmcneill#define R8A7740_CLK_PLLC1 2 151.1Sjmcneill#define R8A7740_CLK_PLLC2 3 161.1Sjmcneill#define R8A7740_CLK_R 4 171.1Sjmcneill#define R8A7740_CLK_USB24S 5 181.1Sjmcneill#define R8A7740_CLK_I 6 191.1Sjmcneill#define R8A7740_CLK_ZG 7 201.1Sjmcneill#define R8A7740_CLK_B 8 211.1Sjmcneill#define R8A7740_CLK_M1 9 221.1Sjmcneill#define R8A7740_CLK_HP 10 231.1Sjmcneill#define R8A7740_CLK_HPP 11 241.1Sjmcneill#define R8A7740_CLK_USBP 12 251.1Sjmcneill#define R8A7740_CLK_S 13 261.1Sjmcneill#define R8A7740_CLK_ZB 14 271.1Sjmcneill#define R8A7740_CLK_M3 15 281.1Sjmcneill#define R8A7740_CLK_CP 16 291.1Sjmcneill 301.1Sjmcneill/* MSTP1 */ 311.1Sjmcneill#define R8A7740_CLK_CEU21 28 321.1Sjmcneill#define R8A7740_CLK_CEU20 27 331.1Sjmcneill#define R8A7740_CLK_TMU0 25 341.1Sjmcneill#define R8A7740_CLK_LCDC1 17 351.1Sjmcneill#define R8A7740_CLK_IIC0 16 361.1Sjmcneill#define R8A7740_CLK_TMU1 11 371.1Sjmcneill#define R8A7740_CLK_LCDC0 0 381.1Sjmcneill 391.1Sjmcneill/* MSTP2 */ 401.1Sjmcneill#define R8A7740_CLK_SCIFA6 30 411.1Sjmcneill#define R8A7740_CLK_INTCA 29 421.1Sjmcneill#define R8A7740_CLK_SCIFA7 22 431.1Sjmcneill#define R8A7740_CLK_DMAC1 18 441.1Sjmcneill#define R8A7740_CLK_DMAC2 17 451.1Sjmcneill#define R8A7740_CLK_DMAC3 16 461.1Sjmcneill#define R8A7740_CLK_USBDMAC 14 471.1Sjmcneill#define R8A7740_CLK_SCIFA5 7 481.1Sjmcneill#define R8A7740_CLK_SCIFB 6 491.1Sjmcneill#define R8A7740_CLK_SCIFA0 4 501.1Sjmcneill#define R8A7740_CLK_SCIFA1 3 511.1Sjmcneill#define R8A7740_CLK_SCIFA2 2 521.1Sjmcneill#define R8A7740_CLK_SCIFA3 1 531.1Sjmcneill#define R8A7740_CLK_SCIFA4 0 541.1Sjmcneill 551.1Sjmcneill/* MSTP3 */ 561.1Sjmcneill#define R8A7740_CLK_CMT1 29 571.1Sjmcneill#define R8A7740_CLK_FSI 28 581.1Sjmcneill#define R8A7740_CLK_IIC1 23 591.1Sjmcneill#define R8A7740_CLK_USBF 20 601.1Sjmcneill#define R8A7740_CLK_SDHI0 14 611.1Sjmcneill#define R8A7740_CLK_SDHI1 13 621.1Sjmcneill#define R8A7740_CLK_MMC 12 631.1Sjmcneill#define R8A7740_CLK_GETHER 9 641.1Sjmcneill#define R8A7740_CLK_TPU0 4 651.1Sjmcneill 661.1Sjmcneill/* MSTP4 */ 671.1Sjmcneill#define R8A7740_CLK_USBH 16 681.1Sjmcneill#define R8A7740_CLK_SDHI2 15 691.1Sjmcneill#define R8A7740_CLK_USBFUNC 7 701.1Sjmcneill#define R8A7740_CLK_USBPHY 6 711.1Sjmcneill 721.1Sjmcneill/* SUBCK* */ 731.1Sjmcneill#define R8A7740_CLK_SUBCK 9 741.1Sjmcneill#define R8A7740_CLK_SUBCK2 10 751.1Sjmcneill 761.1Sjmcneill#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ 77