r8a779f0-cpg-mssr.h revision 1.1.1.1 
1/*	$NetBSD: r8a779f0-cpg-mssr.h,v 1.1.1.1 2026/01/18 05:21:38 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
4/*
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
8#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
9
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11
12/* r8a779f0 CPG Core Clocks */
13
14#define R8A779F0_CLK_ZX			0
15#define R8A779F0_CLK_ZS			1
16#define R8A779F0_CLK_ZT			2
17#define R8A779F0_CLK_ZTR		3
18#define R8A779F0_CLK_S0D2		4
19#define R8A779F0_CLK_S0D3		5
20#define R8A779F0_CLK_S0D4		6
21#define R8A779F0_CLK_S0D2_MM		7
22#define R8A779F0_CLK_S0D3_MM		8
23#define R8A779F0_CLK_S0D4_MM		9
24#define R8A779F0_CLK_S0D2_RT		10
25#define R8A779F0_CLK_S0D3_RT		11
26#define R8A779F0_CLK_S0D4_RT		12
27#define R8A779F0_CLK_S0D6_RT		13
28#define R8A779F0_CLK_S0D3_PER		14
29#define R8A779F0_CLK_S0D6_PER		15
30#define R8A779F0_CLK_S0D12_PER		16
31#define R8A779F0_CLK_S0D24_PER		17
32#define R8A779F0_CLK_S0D2_HSC		18
33#define R8A779F0_CLK_S0D3_HSC		19
34#define R8A779F0_CLK_S0D4_HSC		20
35#define R8A779F0_CLK_S0D6_HSC		21
36#define R8A779F0_CLK_S0D12_HSC		22
37#define R8A779F0_CLK_S0D2_CC		23
38#define R8A779F0_CLK_CL			24
39#define R8A779F0_CLK_CL16M		25
40#define R8A779F0_CLK_CL16M_MM		26
41#define R8A779F0_CLK_CL16M_RT		27
42#define R8A779F0_CLK_CL16M_PER		28
43#define R8A779F0_CLK_CL16M_HSC		29
44#define R8A779F0_CLK_Z0			30
45#define R8A779F0_CLK_Z1			31
46#define R8A779F0_CLK_ZB3		32
47#define R8A779F0_CLK_ZB3D2		33
48#define R8A779F0_CLK_ZB3D4		34
49#define R8A779F0_CLK_SD0H		35
50#define R8A779F0_CLK_SD0		36
51#define R8A779F0_CLK_RPC		37
52#define R8A779F0_CLK_RPCD2		38
53#define R8A779F0_CLK_MSO		39
54#define R8A779F0_CLK_SASYNCRT		40
55#define R8A779F0_CLK_SASYNCPERD1	41
56#define R8A779F0_CLK_SASYNCPERD2	42
57#define R8A779F0_CLK_SASYNCPERD4	43
58#define R8A779F0_CLK_DBGSOC_HSC		44
59#define R8A779F0_CLK_RSW2		45
60#define R8A779F0_CLK_OSC		46
61#define R8A779F0_CLK_ZR			47
62#define R8A779F0_CLK_CPEX		48
63#define R8A779F0_CLK_CBFUSA		49
64#define R8A779F0_CLK_R			50
65
66#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
67