r9a07g054-cpg.h revision 1.1.1.1
1/* $NetBSD: r9a07g054-cpg.h,v 1.1.1.1 2026/01/18 05:21:38 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ 8#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ 9 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/* R9A07G054 CPG Core Clocks */ 13#define R9A07G054_CLK_I 0 14#define R9A07G054_CLK_I2 1 15#define R9A07G054_CLK_G 2 16#define R9A07G054_CLK_S0 3 17#define R9A07G054_CLK_S1 4 18#define R9A07G054_CLK_SPI0 5 19#define R9A07G054_CLK_SPI1 6 20#define R9A07G054_CLK_SD0 7 21#define R9A07G054_CLK_SD1 8 22#define R9A07G054_CLK_M0 9 23#define R9A07G054_CLK_M1 10 24#define R9A07G054_CLK_M2 11 25#define R9A07G054_CLK_M3 12 26#define R9A07G054_CLK_M4 13 27#define R9A07G054_CLK_HP 14 28#define R9A07G054_CLK_TSU 15 29#define R9A07G054_CLK_ZT 16 30#define R9A07G054_CLK_P0 17 31#define R9A07G054_CLK_P1 18 32#define R9A07G054_CLK_P2 19 33#define R9A07G054_CLK_AT 20 34#define R9A07G054_OSCCLK 21 35#define R9A07G054_CLK_P0_DIV2 22 36#define R9A07G054_CLK_DRP_M 23 37#define R9A07G054_CLK_DRP_D 24 38#define R9A07G054_CLK_DRP_A 25 39 40/* R9A07G054 Module Clocks */ 41#define R9A07G054_CA55_SCLK 0 42#define R9A07G054_CA55_PCLK 1 43#define R9A07G054_CA55_ATCLK 2 44#define R9A07G054_CA55_GICCLK 3 45#define R9A07G054_CA55_PERICLK 4 46#define R9A07G054_CA55_ACLK 5 47#define R9A07G054_CA55_TSCLK 6 48#define R9A07G054_GIC600_GICCLK 7 49#define R9A07G054_IA55_CLK 8 50#define R9A07G054_IA55_PCLK 9 51#define R9A07G054_MHU_PCLK 10 52#define R9A07G054_SYC_CNT_CLK 11 53#define R9A07G054_DMAC_ACLK 12 54#define R9A07G054_DMAC_PCLK 13 55#define R9A07G054_OSTM0_PCLK 14 56#define R9A07G054_OSTM1_PCLK 15 57#define R9A07G054_OSTM2_PCLK 16 58#define R9A07G054_MTU_X_MCK_MTU3 17 59#define R9A07G054_POE3_CLKM_POE 18 60#define R9A07G054_GPT_PCLK 19 61#define R9A07G054_POEG_A_CLKP 20 62#define R9A07G054_POEG_B_CLKP 21 63#define R9A07G054_POEG_C_CLKP 22 64#define R9A07G054_POEG_D_CLKP 23 65#define R9A07G054_WDT0_PCLK 24 66#define R9A07G054_WDT0_CLK 25 67#define R9A07G054_WDT1_PCLK 26 68#define R9A07G054_WDT1_CLK 27 69#define R9A07G054_WDT2_PCLK 28 70#define R9A07G054_WDT2_CLK 29 71#define R9A07G054_SPI_CLK2 30 72#define R9A07G054_SPI_CLK 31 73#define R9A07G054_SDHI0_IMCLK 32 74#define R9A07G054_SDHI0_IMCLK2 33 75#define R9A07G054_SDHI0_CLK_HS 34 76#define R9A07G054_SDHI0_ACLK 35 77#define R9A07G054_SDHI1_IMCLK 36 78#define R9A07G054_SDHI1_IMCLK2 37 79#define R9A07G054_SDHI1_CLK_HS 38 80#define R9A07G054_SDHI1_ACLK 39 81#define R9A07G054_GPU_CLK 40 82#define R9A07G054_GPU_AXI_CLK 41 83#define R9A07G054_GPU_ACE_CLK 42 84#define R9A07G054_ISU_ACLK 43 85#define R9A07G054_ISU_PCLK 44 86#define R9A07G054_H264_CLK_A 45 87#define R9A07G054_H264_CLK_P 46 88#define R9A07G054_CRU_SYSCLK 47 89#define R9A07G054_CRU_VCLK 48 90#define R9A07G054_CRU_PCLK 49 91#define R9A07G054_CRU_ACLK 50 92#define R9A07G054_MIPI_DSI_PLLCLK 51 93#define R9A07G054_MIPI_DSI_SYSCLK 52 94#define R9A07G054_MIPI_DSI_ACLK 53 95#define R9A07G054_MIPI_DSI_PCLK 54 96#define R9A07G054_MIPI_DSI_VCLK 55 97#define R9A07G054_MIPI_DSI_LPCLK 56 98#define R9A07G054_LCDC_CLK_A 57 99#define R9A07G054_LCDC_CLK_P 58 100#define R9A07G054_LCDC_CLK_D 59 101#define R9A07G054_SSI0_PCLK2 60 102#define R9A07G054_SSI0_PCLK_SFR 61 103#define R9A07G054_SSI1_PCLK2 62 104#define R9A07G054_SSI1_PCLK_SFR 63 105#define R9A07G054_SSI2_PCLK2 64 106#define R9A07G054_SSI2_PCLK_SFR 65 107#define R9A07G054_SSI3_PCLK2 66 108#define R9A07G054_SSI3_PCLK_SFR 67 109#define R9A07G054_SRC_CLKP 68 110#define R9A07G054_USB_U2H0_HCLK 69 111#define R9A07G054_USB_U2H1_HCLK 70 112#define R9A07G054_USB_U2P_EXR_CPUCLK 71 113#define R9A07G054_USB_PCLK 72 114#define R9A07G054_ETH0_CLK_AXI 73 115#define R9A07G054_ETH0_CLK_CHI 74 116#define R9A07G054_ETH1_CLK_AXI 75 117#define R9A07G054_ETH1_CLK_CHI 76 118#define R9A07G054_I2C0_PCLK 77 119#define R9A07G054_I2C1_PCLK 78 120#define R9A07G054_I2C2_PCLK 79 121#define R9A07G054_I2C3_PCLK 80 122#define R9A07G054_SCIF0_CLK_PCK 81 123#define R9A07G054_SCIF1_CLK_PCK 82 124#define R9A07G054_SCIF2_CLK_PCK 83 125#define R9A07G054_SCIF3_CLK_PCK 84 126#define R9A07G054_SCIF4_CLK_PCK 85 127#define R9A07G054_SCI0_CLKP 86 128#define R9A07G054_SCI1_CLKP 87 129#define R9A07G054_IRDA_CLKP 88 130#define R9A07G054_RSPI0_CLKB 89 131#define R9A07G054_RSPI1_CLKB 90 132#define R9A07G054_RSPI2_CLKB 91 133#define R9A07G054_CANFD_PCLK 92 134#define R9A07G054_GPIO_HCLK 93 135#define R9A07G054_ADC_ADCLK 94 136#define R9A07G054_ADC_PCLK 95 137#define R9A07G054_TSU_PCLK 96 138#define R9A07G054_STPAI_INITCLK 97 139#define R9A07G054_STPAI_ACLK 98 140#define R9A07G054_STPAI_MCLK 99 141#define R9A07G054_STPAI_DCLKIN 100 142#define R9A07G054_STPAI_ACLK_DRP 101 143 144/* R9A07G054 Resets */ 145#define R9A07G054_CA55_RST_1_0 0 146#define R9A07G054_CA55_RST_1_1 1 147#define R9A07G054_CA55_RST_3_0 2 148#define R9A07G054_CA55_RST_3_1 3 149#define R9A07G054_CA55_RST_4 4 150#define R9A07G054_CA55_RST_5 5 151#define R9A07G054_CA55_RST_6 6 152#define R9A07G054_CA55_RST_7 7 153#define R9A07G054_CA55_RST_8 8 154#define R9A07G054_CA55_RST_9 9 155#define R9A07G054_CA55_RST_10 10 156#define R9A07G054_CA55_RST_11 11 157#define R9A07G054_CA55_RST_12 12 158#define R9A07G054_GIC600_GICRESET_N 13 159#define R9A07G054_GIC600_DBG_GICRESET_N 14 160#define R9A07G054_IA55_RESETN 15 161#define R9A07G054_MHU_RESETN 16 162#define R9A07G054_DMAC_ARESETN 17 163#define R9A07G054_DMAC_RST_ASYNC 18 164#define R9A07G054_SYC_RESETN 19 165#define R9A07G054_OSTM0_PRESETZ 20 166#define R9A07G054_OSTM1_PRESETZ 21 167#define R9A07G054_OSTM2_PRESETZ 22 168#define R9A07G054_MTU_X_PRESET_MTU3 23 169#define R9A07G054_POE3_RST_M_REG 24 170#define R9A07G054_GPT_RST_C 25 171#define R9A07G054_POEG_A_RST 26 172#define R9A07G054_POEG_B_RST 27 173#define R9A07G054_POEG_C_RST 28 174#define R9A07G054_POEG_D_RST 29 175#define R9A07G054_WDT0_PRESETN 30 176#define R9A07G054_WDT1_PRESETN 31 177#define R9A07G054_WDT2_PRESETN 32 178#define R9A07G054_SPI_RST 33 179#define R9A07G054_SDHI0_IXRST 34 180#define R9A07G054_SDHI1_IXRST 35 181#define R9A07G054_GPU_RESETN 36 182#define R9A07G054_GPU_AXI_RESETN 37 183#define R9A07G054_GPU_ACE_RESETN 38 184#define R9A07G054_ISU_ARESETN 39 185#define R9A07G054_ISU_PRESETN 40 186#define R9A07G054_H264_X_RESET_VCP 41 187#define R9A07G054_H264_CP_PRESET_P 42 188#define R9A07G054_CRU_CMN_RSTB 43 189#define R9A07G054_CRU_PRESETN 44 190#define R9A07G054_CRU_ARESETN 45 191#define R9A07G054_MIPI_DSI_CMN_RSTB 46 192#define R9A07G054_MIPI_DSI_ARESET_N 47 193#define R9A07G054_MIPI_DSI_PRESET_N 48 194#define R9A07G054_LCDC_RESET_N 49 195#define R9A07G054_SSI0_RST_M2_REG 50 196#define R9A07G054_SSI1_RST_M2_REG 51 197#define R9A07G054_SSI2_RST_M2_REG 52 198#define R9A07G054_SSI3_RST_M2_REG 53 199#define R9A07G054_SRC_RST 54 200#define R9A07G054_USB_U2H0_HRESETN 55 201#define R9A07G054_USB_U2H1_HRESETN 56 202#define R9A07G054_USB_U2P_EXL_SYSRST 57 203#define R9A07G054_USB_PRESETN 58 204#define R9A07G054_ETH0_RST_HW_N 59 205#define R9A07G054_ETH1_RST_HW_N 60 206#define R9A07G054_I2C0_MRST 61 207#define R9A07G054_I2C1_MRST 62 208#define R9A07G054_I2C2_MRST 63 209#define R9A07G054_I2C3_MRST 64 210#define R9A07G054_SCIF0_RST_SYSTEM_N 65 211#define R9A07G054_SCIF1_RST_SYSTEM_N 66 212#define R9A07G054_SCIF2_RST_SYSTEM_N 67 213#define R9A07G054_SCIF3_RST_SYSTEM_N 68 214#define R9A07G054_SCIF4_RST_SYSTEM_N 69 215#define R9A07G054_SCI0_RST 70 216#define R9A07G054_SCI1_RST 71 217#define R9A07G054_IRDA_RST 72 218#define R9A07G054_RSPI0_RST 73 219#define R9A07G054_RSPI1_RST 74 220#define R9A07G054_RSPI2_RST 75 221#define R9A07G054_CANFD_RSTP_N 76 222#define R9A07G054_CANFD_RSTC_N 77 223#define R9A07G054_GPIO_RSTN 78 224#define R9A07G054_GPIO_PORT_RESETN 79 225#define R9A07G054_GPIO_SPARE_RESETN 80 226#define R9A07G054_ADC_PRESETN 81 227#define R9A07G054_ADC_ADRST_N 82 228#define R9A07G054_TSU_PRESETN 83 229#define R9A07G054_STPAI_ARESETN 84 230 231/* Power domain IDs. */ 232#define R9A07G054_PD_ALWAYS_ON 0 233#define R9A07G054_PD_GIC 1 234#define R9A07G054_PD_IA55 2 235#define R9A07G054_PD_MHU 3 236#define R9A07G054_PD_CORESIGHT 4 237#define R9A07G054_PD_SYC 5 238#define R9A07G054_PD_DMAC 6 239#define R9A07G054_PD_GTM0 7 240#define R9A07G054_PD_GTM1 8 241#define R9A07G054_PD_GTM2 9 242#define R9A07G054_PD_MTU 10 243#define R9A07G054_PD_POE3 11 244#define R9A07G054_PD_GPT 12 245#define R9A07G054_PD_POEGA 13 246#define R9A07G054_PD_POEGB 14 247#define R9A07G054_PD_POEGC 15 248#define R9A07G054_PD_POEGD 16 249#define R9A07G054_PD_WDT0 17 250#define R9A07G054_PD_WDT1 18 251#define R9A07G054_PD_SPI 19 252#define R9A07G054_PD_SDHI0 20 253#define R9A07G054_PD_SDHI1 21 254#define R9A07G054_PD_3DGE 22 255#define R9A07G054_PD_ISU 23 256#define R9A07G054_PD_VCPL4 24 257#define R9A07G054_PD_CRU 25 258#define R9A07G054_PD_MIPI_DSI 26 259#define R9A07G054_PD_LCDC 27 260#define R9A07G054_PD_SSI0 28 261#define R9A07G054_PD_SSI1 29 262#define R9A07G054_PD_SSI2 30 263#define R9A07G054_PD_SSI3 31 264#define R9A07G054_PD_SRC 32 265#define R9A07G054_PD_USB0 33 266#define R9A07G054_PD_USB1 34 267#define R9A07G054_PD_USB_PHY 35 268#define R9A07G054_PD_ETHER0 36 269#define R9A07G054_PD_ETHER1 37 270#define R9A07G054_PD_I2C0 38 271#define R9A07G054_PD_I2C1 39 272#define R9A07G054_PD_I2C2 40 273#define R9A07G054_PD_I2C3 41 274#define R9A07G054_PD_SCIF0 42 275#define R9A07G054_PD_SCIF1 43 276#define R9A07G054_PD_SCIF2 44 277#define R9A07G054_PD_SCIF3 45 278#define R9A07G054_PD_SCIF4 46 279#define R9A07G054_PD_SCI0 47 280#define R9A07G054_PD_SCI1 48 281#define R9A07G054_PD_IRDA 49 282#define R9A07G054_PD_RSPI0 50 283#define R9A07G054_PD_RSPI1 51 284#define R9A07G054_PD_RSPI2 52 285#define R9A07G054_PD_CANFD 53 286#define R9A07G054_PD_ADC 54 287#define R9A07G054_PD_TSU 55 288 289#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ 290