r9a08g045-cpg.h revision 1.1.1.1
1/* $NetBSD: r9a08g045-cpg.h,v 1.1.1.1 2026/01/18 05:21:38 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7#ifndef __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ 8#define __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ 9 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/* R9A08G045 CPG Core Clocks */ 13#define R9A08G045_CLK_I 0 14#define R9A08G045_CLK_I2 1 15#define R9A08G045_CLK_I3 2 16#define R9A08G045_CLK_S0 3 17#define R9A08G045_CLK_SPI0 4 18#define R9A08G045_CLK_SPI1 5 19#define R9A08G045_CLK_SD0 6 20#define R9A08G045_CLK_SD1 7 21#define R9A08G045_CLK_SD2 8 22#define R9A08G045_CLK_M0 9 23#define R9A08G045_CLK_HP 10 24#define R9A08G045_CLK_TSU 11 25#define R9A08G045_CLK_ZT 12 26#define R9A08G045_CLK_P0 13 27#define R9A08G045_CLK_P1 14 28#define R9A08G045_CLK_P2 15 29#define R9A08G045_CLK_P3 16 30#define R9A08G045_CLK_P4 17 31#define R9A08G045_CLK_P5 18 32#define R9A08G045_CLK_AT 19 33#define R9A08G045_CLK_OC0 20 34#define R9A08G045_CLK_OC1 21 35#define R9A08G045_OSCCLK 22 36#define R9A08G045_OSCCLK2 23 37#define R9A08G045_SWD 24 38 39/* R9A08G045 Module Clocks */ 40#define R9A08G045_OCTA_ACLK 0 41#define R9A08G045_OCTA_MCLK 1 42#define R9A08G045_CA55_SCLK 2 43#define R9A08G045_CA55_PCLK 3 44#define R9A08G045_CA55_ATCLK 4 45#define R9A08G045_CA55_GICCLK 5 46#define R9A08G045_CA55_PERICLK 6 47#define R9A08G045_CA55_ACLK 7 48#define R9A08G045_CA55_TSCLK 8 49#define R9A08G045_SRAM_ACPU_ACLK0 9 50#define R9A08G045_SRAM_ACPU_ACLK1 10 51#define R9A08G045_SRAM_ACPU_ACLK2 11 52#define R9A08G045_GIC600_GICCLK 12 53#define R9A08G045_IA55_CLK 13 54#define R9A08G045_IA55_PCLK 14 55#define R9A08G045_MHU_PCLK 15 56#define R9A08G045_SYC_CNT_CLK 16 57#define R9A08G045_DMAC_ACLK 17 58#define R9A08G045_DMAC_PCLK 18 59#define R9A08G045_OSTM0_PCLK 19 60#define R9A08G045_OSTM1_PCLK 20 61#define R9A08G045_OSTM2_PCLK 21 62#define R9A08G045_OSTM3_PCLK 22 63#define R9A08G045_OSTM4_PCLK 23 64#define R9A08G045_OSTM5_PCLK 24 65#define R9A08G045_OSTM6_PCLK 25 66#define R9A08G045_OSTM7_PCLK 26 67#define R9A08G045_MTU_X_MCK_MTU3 27 68#define R9A08G045_POE3_CLKM_POE 28 69#define R9A08G045_GPT_PCLK 29 70#define R9A08G045_POEG_A_CLKP 30 71#define R9A08G045_POEG_B_CLKP 31 72#define R9A08G045_POEG_C_CLKP 32 73#define R9A08G045_POEG_D_CLKP 33 74#define R9A08G045_WDT0_PCLK 34 75#define R9A08G045_WDT0_CLK 35 76#define R9A08G045_WDT1_PCLK 36 77#define R9A08G045_WDT1_CLK 37 78#define R9A08G045_WDT2_PCLK 38 79#define R9A08G045_WDT2_CLK 39 80#define R9A08G045_SPI_HCLK 40 81#define R9A08G045_SPI_ACLK 41 82#define R9A08G045_SPI_CLK 42 83#define R9A08G045_SPI_CLKX2 43 84#define R9A08G045_SDHI0_IMCLK 44 85#define R9A08G045_SDHI0_IMCLK2 45 86#define R9A08G045_SDHI0_CLK_HS 46 87#define R9A08G045_SDHI0_ACLK 47 88#define R9A08G045_SDHI1_IMCLK 48 89#define R9A08G045_SDHI1_IMCLK2 49 90#define R9A08G045_SDHI1_CLK_HS 50 91#define R9A08G045_SDHI1_ACLK 51 92#define R9A08G045_SDHI2_IMCLK 52 93#define R9A08G045_SDHI2_IMCLK2 53 94#define R9A08G045_SDHI2_CLK_HS 54 95#define R9A08G045_SDHI2_ACLK 55 96#define R9A08G045_SSI0_PCLK2 56 97#define R9A08G045_SSI0_PCLK_SFR 57 98#define R9A08G045_SSI1_PCLK2 58 99#define R9A08G045_SSI1_PCLK_SFR 59 100#define R9A08G045_SSI2_PCLK2 60 101#define R9A08G045_SSI2_PCLK_SFR 61 102#define R9A08G045_SSI3_PCLK2 62 103#define R9A08G045_SSI3_PCLK_SFR 63 104#define R9A08G045_SRC_CLKP 64 105#define R9A08G045_USB_U2H0_HCLK 65 106#define R9A08G045_USB_U2H1_HCLK 66 107#define R9A08G045_USB_U2P_EXR_CPUCLK 67 108#define R9A08G045_USB_PCLK 68 109#define R9A08G045_ETH0_CLK_AXI 69 110#define R9A08G045_ETH0_CLK_CHI 70 111#define R9A08G045_ETH0_REFCLK 71 112#define R9A08G045_ETH1_CLK_AXI 72 113#define R9A08G045_ETH1_CLK_CHI 73 114#define R9A08G045_ETH1_REFCLK 74 115#define R9A08G045_I2C0_PCLK 75 116#define R9A08G045_I2C1_PCLK 76 117#define R9A08G045_I2C2_PCLK 77 118#define R9A08G045_I2C3_PCLK 78 119#define R9A08G045_SCIF0_CLK_PCK 79 120#define R9A08G045_SCIF1_CLK_PCK 80 121#define R9A08G045_SCIF2_CLK_PCK 81 122#define R9A08G045_SCIF3_CLK_PCK 82 123#define R9A08G045_SCIF4_CLK_PCK 83 124#define R9A08G045_SCIF5_CLK_PCK 84 125#define R9A08G045_SCI0_CLKP 85 126#define R9A08G045_SCI1_CLKP 86 127#define R9A08G045_IRDA_CLKP 87 128#define R9A08G045_RSPI0_CLKB 88 129#define R9A08G045_RSPI1_CLKB 89 130#define R9A08G045_RSPI2_CLKB 90 131#define R9A08G045_RSPI3_CLKB 91 132#define R9A08G045_RSPI4_CLKB 92 133#define R9A08G045_CANFD_PCLK 93 134#define R9A08G045_CANFD_CLK_RAM 94 135#define R9A08G045_GPIO_HCLK 95 136#define R9A08G045_ADC_ADCLK 96 137#define R9A08G045_ADC_PCLK 97 138#define R9A08G045_TSU_PCLK 98 139#define R9A08G045_PDM_PCLK 99 140#define R9A08G045_PDM_CCLK 100 141#define R9A08G045_PCI_ACLK 101 142#define R9A08G045_PCI_CLKL1PM 102 143#define R9A08G045_SPDIF_PCLK 103 144#define R9A08G045_I3C_PCLK 104 145#define R9A08G045_I3C_TCLK 105 146#define R9A08G045_VBAT_BCLK 106 147 148/* R9A08G045 Resets */ 149#define R9A08G045_CA55_RST_1_0 0 150#define R9A08G045_CA55_RST_3_0 1 151#define R9A08G045_CA55_RST_4 2 152#define R9A08G045_CA55_RST_5 3 153#define R9A08G045_CA55_RST_6 4 154#define R9A08G045_CA55_RST_7 5 155#define R9A08G045_CA55_RST_8 6 156#define R9A08G045_CA55_RST_9 7 157#define R9A08G045_CA55_RST_10 8 158#define R9A08G045_CA55_RST_11 9 159#define R9A08G045_CA55_RST_12 10 160#define R9A08G045_SRAM_ACPU_ARESETN0 11 161#define R9A08G045_SRAM_ACPU_ARESETN1 12 162#define R9A08G045_SRAM_ACPU_ARESETN2 13 163#define R9A08G045_GIC600_GICRESET_N 14 164#define R9A08G045_GIC600_DBG_GICRESET_N 15 165#define R9A08G045_IA55_RESETN 16 166#define R9A08G045_MHU_RESETN 17 167#define R9A08G045_DMAC_ARESETN 18 168#define R9A08G045_DMAC_RST_ASYNC 19 169#define R9A08G045_SYC_RESETN 20 170#define R9A08G045_OSTM0_PRESETZ 21 171#define R9A08G045_OSTM1_PRESETZ 22 172#define R9A08G045_OSTM2_PRESETZ 23 173#define R9A08G045_OSTM3_PRESETZ 24 174#define R9A08G045_OSTM4_PRESETZ 25 175#define R9A08G045_OSTM5_PRESETZ 26 176#define R9A08G045_OSTM6_PRESETZ 27 177#define R9A08G045_OSTM7_PRESETZ 28 178#define R9A08G045_MTU_X_PRESET_MTU3 29 179#define R9A08G045_POE3_RST_M_REG 30 180#define R9A08G045_GPT_RST_C 31 181#define R9A08G045_POEG_A_RST 32 182#define R9A08G045_POEG_B_RST 33 183#define R9A08G045_POEG_C_RST 34 184#define R9A08G045_POEG_D_RST 35 185#define R9A08G045_WDT0_PRESETN 36 186#define R9A08G045_WDT1_PRESETN 37 187#define R9A08G045_WDT2_PRESETN 38 188#define R9A08G045_SPI_HRESETN 39 189#define R9A08G045_SPI_ARESETN 40 190#define R9A08G045_SDHI0_IXRST 41 191#define R9A08G045_SDHI1_IXRST 42 192#define R9A08G045_SDHI2_IXRST 43 193#define R9A08G045_SSI0_RST_M2_REG 44 194#define R9A08G045_SSI1_RST_M2_REG 45 195#define R9A08G045_SSI2_RST_M2_REG 46 196#define R9A08G045_SSI3_RST_M2_REG 47 197#define R9A08G045_SRC_RST 48 198#define R9A08G045_USB_U2H0_HRESETN 49 199#define R9A08G045_USB_U2H1_HRESETN 50 200#define R9A08G045_USB_U2P_EXL_SYSRST 51 201#define R9A08G045_USB_PRESETN 52 202#define R9A08G045_ETH0_RST_HW_N 53 203#define R9A08G045_ETH1_RST_HW_N 54 204#define R9A08G045_I2C0_MRST 55 205#define R9A08G045_I2C1_MRST 56 206#define R9A08G045_I2C2_MRST 57 207#define R9A08G045_I2C3_MRST 58 208#define R9A08G045_SCIF0_RST_SYSTEM_N 59 209#define R9A08G045_SCIF1_RST_SYSTEM_N 60 210#define R9A08G045_SCIF2_RST_SYSTEM_N 61 211#define R9A08G045_SCIF3_RST_SYSTEM_N 62 212#define R9A08G045_SCIF4_RST_SYSTEM_N 63 213#define R9A08G045_SCIF5_RST_SYSTEM_N 64 214#define R9A08G045_SCI0_RST 65 215#define R9A08G045_SCI1_RST 66 216#define R9A08G045_IRDA_RST 67 217#define R9A08G045_RSPI0_RST 68 218#define R9A08G045_RSPI1_RST 69 219#define R9A08G045_RSPI2_RST 70 220#define R9A08G045_RSPI3_RST 71 221#define R9A08G045_RSPI4_RST 72 222#define R9A08G045_CANFD_RSTP_N 73 223#define R9A08G045_CANFD_RSTC_N 74 224#define R9A08G045_GPIO_RSTN 75 225#define R9A08G045_GPIO_PORT_RESETN 76 226#define R9A08G045_GPIO_SPARE_RESETN 77 227#define R9A08G045_ADC_PRESETN 78 228#define R9A08G045_ADC_ADRST_N 79 229#define R9A08G045_TSU_PRESETN 80 230#define R9A08G045_OCTA_ARESETN 81 231#define R9A08G045_PDM0_PRESETNT 82 232#define R9A08G045_PCI_ARESETN 83 233#define R9A08G045_PCI_RST_B 84 234#define R9A08G045_PCI_RST_GP_B 85 235#define R9A08G045_PCI_RST_PS_B 86 236#define R9A08G045_PCI_RST_RSM_B 87 237#define R9A08G045_PCI_RST_CFG_B 88 238#define R9A08G045_PCI_RST_LOAD_B 89 239#define R9A08G045_SPDIF_RST 90 240#define R9A08G045_I3C_TRESETN 91 241#define R9A08G045_I3C_PRESETN 92 242#define R9A08G045_VBAT_BRESETN 93 243 244/* Power domain IDs. */ 245#define R9A08G045_PD_ALWAYS_ON 0 246#define R9A08G045_PD_GIC 1 247#define R9A08G045_PD_IA55 2 248#define R9A08G045_PD_MHU 3 249#define R9A08G045_PD_CORESIGHT 4 250#define R9A08G045_PD_SYC 5 251#define R9A08G045_PD_DMAC 6 252#define R9A08G045_PD_GTM0 7 253#define R9A08G045_PD_GTM1 8 254#define R9A08G045_PD_GTM2 9 255#define R9A08G045_PD_GTM3 10 256#define R9A08G045_PD_GTM4 11 257#define R9A08G045_PD_GTM5 12 258#define R9A08G045_PD_GTM6 13 259#define R9A08G045_PD_GTM7 14 260#define R9A08G045_PD_MTU 15 261#define R9A08G045_PD_POE3 16 262#define R9A08G045_PD_GPT 17 263#define R9A08G045_PD_POEGA 18 264#define R9A08G045_PD_POEGB 19 265#define R9A08G045_PD_POEGC 20 266#define R9A08G045_PD_POEGD 21 267#define R9A08G045_PD_WDT0 22 268#define R9A08G045_PD_XSPI 23 269#define R9A08G045_PD_SDHI0 24 270#define R9A08G045_PD_SDHI1 25 271#define R9A08G045_PD_SDHI2 26 272#define R9A08G045_PD_SSI0 27 273#define R9A08G045_PD_SSI1 28 274#define R9A08G045_PD_SSI2 29 275#define R9A08G045_PD_SSI3 30 276#define R9A08G045_PD_SRC 31 277#define R9A08G045_PD_USB0 32 278#define R9A08G045_PD_USB1 33 279#define R9A08G045_PD_USB_PHY 34 280#define R9A08G045_PD_ETHER0 35 281#define R9A08G045_PD_ETHER1 36 282#define R9A08G045_PD_I2C0 37 283#define R9A08G045_PD_I2C1 38 284#define R9A08G045_PD_I2C2 39 285#define R9A08G045_PD_I2C3 40 286#define R9A08G045_PD_SCIF0 41 287#define R9A08G045_PD_SCIF1 42 288#define R9A08G045_PD_SCIF2 43 289#define R9A08G045_PD_SCIF3 44 290#define R9A08G045_PD_SCIF4 45 291#define R9A08G045_PD_SCIF5 46 292#define R9A08G045_PD_SCI0 47 293#define R9A08G045_PD_SCI1 48 294#define R9A08G045_PD_IRDA 49 295#define R9A08G045_PD_RSPI0 50 296#define R9A08G045_PD_RSPI1 51 297#define R9A08G045_PD_RSPI2 52 298#define R9A08G045_PD_RSPI3 53 299#define R9A08G045_PD_RSPI4 54 300#define R9A08G045_PD_CANFD 55 301#define R9A08G045_PD_ADC 56 302#define R9A08G045_PD_TSU 57 303#define R9A08G045_PD_OCTA 58 304#define R9A08G045_PD_PDM 59 305#define R9A08G045_PD_PCI 60 306#define R9A08G045_PD_SPDIF 61 307#define R9A08G045_PD_I3C 62 308#define R9A08G045_PD_VBAT 63 309 310#define R9A08G045_PD_DDR 64 311#define R9A08G045_PD_TZCDDR 65 312#define R9A08G045_PD_OTFDE_DDR 66 313 314#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ 315