rockchip,rv1126-cru.h revision 1.1.1.1
1/* $NetBSD: rockchip,rv1126-cru.h,v 1.1.1.1 2026/01/18 05:21:40 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 4/* 5 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 6 * Author: Finley Xiao <finley.xiao@rock-chips.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 11 12/* pmucru-clocks indices */ 13 14/* pll clocks */ 15#define PLL_GPLL 1 16 17/* sclk (special clocks) */ 18#define CLK_OSC0_DIV32K 2 19#define CLK_RTC32K 3 20#define CLK_WIFI_DIV 4 21#define CLK_WIFI_OSC0 5 22#define CLK_WIFI 6 23#define CLK_PMU 7 24#define SCLK_UART1_DIV 8 25#define SCLK_UART1_FRACDIV 9 26#define SCLK_UART1_MUX 10 27#define SCLK_UART1 11 28#define CLK_I2C0 12 29#define CLK_I2C2 13 30#define CLK_CAPTURE_PWM0 14 31#define CLK_PWM0 15 32#define CLK_CAPTURE_PWM1 16 33#define CLK_PWM1 17 34#define CLK_SPI0 18 35#define DBCLK_GPIO0 19 36#define CLK_PMUPVTM 20 37#define CLK_CORE_PMUPVTM 21 38#define CLK_REF12M 22 39#define CLK_USBPHY_OTG_REF 23 40#define CLK_USBPHY_HOST_REF 24 41#define CLK_REF24M 25 42#define CLK_MIPIDSIPHY_REF 26 43 44/* pclk */ 45#define PCLK_PDPMU 30 46#define PCLK_PMU 31 47#define PCLK_UART1 32 48#define PCLK_I2C0 33 49#define PCLK_I2C2 34 50#define PCLK_PWM0 35 51#define PCLK_PWM1 36 52#define PCLK_SPI0 37 53#define PCLK_GPIO0 38 54#define PCLK_PMUSGRF 39 55#define PCLK_PMUGRF 40 56#define PCLK_PMUCRU 41 57#define PCLK_CHIPVEROTP 42 58#define PCLK_PDPMU_NIU 43 59#define PCLK_PMUPVTM 44 60#define PCLK_SCRKEYGEN 45 61 62#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) 63 64/* cru-clocks indices */ 65 66/* pll clocks */ 67#define PLL_APLL 1 68#define PLL_DPLL 2 69#define PLL_CPLL 3 70#define PLL_HPLL 4 71 72/* sclk (special clocks) */ 73#define ARMCLK 5 74#define USB480M 6 75#define CLK_CORE_CPUPVTM 7 76#define CLK_CPUPVTM 8 77#define CLK_SCR1 9 78#define CLK_SCR1_CORE 10 79#define CLK_SCR1_RTC 11 80#define CLK_SCR1_JTAG 12 81#define SCLK_UART0_DIV 13 82#define SCLK_UART0_FRAC 14 83#define SCLK_UART0_MUX 15 84#define SCLK_UART0 16 85#define SCLK_UART2_DIV 17 86#define SCLK_UART2_FRAC 18 87#define SCLK_UART2_MUX 19 88#define SCLK_UART2 20 89#define SCLK_UART3_DIV 21 90#define SCLK_UART3_FRAC 22 91#define SCLK_UART3_MUX 23 92#define SCLK_UART3 24 93#define SCLK_UART4_DIV 25 94#define SCLK_UART4_FRAC 26 95#define SCLK_UART4_MUX 27 96#define SCLK_UART4 28 97#define SCLK_UART5_DIV 29 98#define SCLK_UART5_FRAC 30 99#define SCLK_UART5_MUX 31 100#define SCLK_UART5 32 101#define CLK_I2C1 33 102#define CLK_I2C3 34 103#define CLK_I2C4 35 104#define CLK_I2C5 36 105#define CLK_SPI1 37 106#define CLK_CAPTURE_PWM2 38 107#define CLK_PWM2 39 108#define DBCLK_GPIO1 40 109#define DBCLK_GPIO2 41 110#define DBCLK_GPIO3 42 111#define DBCLK_GPIO4 43 112#define CLK_SARADC 44 113#define CLK_TIMER0 45 114#define CLK_TIMER1 46 115#define CLK_TIMER2 47 116#define CLK_TIMER3 48 117#define CLK_TIMER4 49 118#define CLK_TIMER5 50 119#define CLK_CAN 51 120#define CLK_NPU_TSADC 52 121#define CLK_NPU_TSADCPHY 53 122#define CLK_CPU_TSADC 54 123#define CLK_CPU_TSADCPHY 55 124#define CLK_CRYPTO_CORE 56 125#define CLK_CRYPTO_PKA 57 126#define MCLK_I2S0_TX_DIV 58 127#define MCLK_I2S0_TX_FRACDIV 59 128#define MCLK_I2S0_TX_MUX 60 129#define MCLK_I2S0_TX 61 130#define MCLK_I2S0_RX_DIV 62 131#define MCLK_I2S0_RX_FRACDIV 63 132#define MCLK_I2S0_RX_MUX 64 133#define MCLK_I2S0_RX 65 134#define MCLK_I2S0_TX_OUT2IO 66 135#define MCLK_I2S0_RX_OUT2IO 67 136#define MCLK_I2S1_DIV 68 137#define MCLK_I2S1_FRACDIV 69 138#define MCLK_I2S1_MUX 70 139#define MCLK_I2S1 71 140#define MCLK_I2S1_OUT2IO 72 141#define MCLK_I2S2_DIV 73 142#define MCLK_I2S2_FRACDIV 74 143#define MCLK_I2S2_MUX 75 144#define MCLK_I2S2 76 145#define MCLK_I2S2_OUT2IO 77 146#define MCLK_PDM 78 147#define SCLK_ADUPWM_DIV 79 148#define SCLK_AUDPWM_FRACDIV 80 149#define SCLK_AUDPWM_MUX 81 150#define SCLK_AUDPWM 82 151#define CLK_ACDCDIG_ADC 83 152#define CLK_ACDCDIG_DAC 84 153#define CLK_ACDCDIG_I2C 85 154#define CLK_VENC_CORE 86 155#define CLK_VDEC_CORE 87 156#define CLK_VDEC_CA 88 157#define CLK_VDEC_HEVC_CA 89 158#define CLK_RGA_CORE 90 159#define CLK_IEP_CORE 91 160#define CLK_ISP_DIV 92 161#define CLK_ISP_NP5 93 162#define CLK_ISP_NUX 94 163#define CLK_ISP 95 164#define CLK_CIF_OUT_DIV 96 165#define CLK_CIF_OUT_FRACDIV 97 166#define CLK_CIF_OUT_MUX 98 167#define CLK_CIF_OUT 99 168#define CLK_MIPICSI_OUT_DIV 100 169#define CLK_MIPICSI_OUT_FRACDIV 101 170#define CLK_MIPICSI_OUT_MUX 102 171#define CLK_MIPICSI_OUT 103 172#define CLK_ISPP_DIV 104 173#define CLK_ISPP_NP5 105 174#define CLK_ISPP_NUX 106 175#define CLK_ISPP 107 176#define CLK_SDMMC 108 177#define SCLK_SDMMC_DRV 109 178#define SCLK_SDMMC_SAMPLE 110 179#define CLK_SDIO 111 180#define SCLK_SDIO_DRV 112 181#define SCLK_SDIO_SAMPLE 113 182#define CLK_EMMC 114 183#define SCLK_EMMC_DRV 115 184#define SCLK_EMMC_SAMPLE 116 185#define CLK_NANDC 117 186#define SCLK_SFC 118 187#define CLK_USBHOST_UTMI_OHCI 119 188#define CLK_USBOTG_REF 120 189#define CLK_GMAC_DIV 121 190#define CLK_GMAC_RGMII_M0 122 191#define CLK_GMAC_SRC_M0 123 192#define CLK_GMAC_RGMII_M1 124 193#define CLK_GMAC_SRC_M1 125 194#define CLK_GMAC_SRC 126 195#define CLK_GMAC_REF 127 196#define CLK_GMAC_TX_SRC 128 197#define CLK_GMAC_TX_DIV5 129 198#define CLK_GMAC_TX_DIV50 130 199#define RGMII_MODE_CLK 131 200#define CLK_GMAC_RX_SRC 132 201#define CLK_GMAC_RX_DIV2 133 202#define CLK_GMAC_RX_DIV20 134 203#define RMII_MODE_CLK 135 204#define CLK_GMAC_TX_RX 136 205#define CLK_GMAC_PTPREF 137 206#define CLK_GMAC_ETHERNET_OUT 138 207#define CLK_DDRPHY 139 208#define CLK_DDR_MON 140 209#define TMCLK_DDR_MON 141 210#define CLK_NPU_DIV 142 211#define CLK_NPU_NP5 143 212#define CLK_CORE_NPU 144 213#define CLK_CORE_NPUPVTM 145 214#define CLK_NPUPVTM 146 215#define SCLK_DDRCLK 147 216#define CLK_OTP 148 217 218/* dclk */ 219#define DCLK_DECOM 150 220#define DCLK_VOP_DIV 151 221#define DCLK_VOP_FRACDIV 152 222#define DCLK_VOP_MUX 153 223#define DCLK_VOP 154 224#define DCLK_CIF 155 225#define DCLK_CIFLITE 156 226 227/* aclk */ 228#define ACLK_PDBUS 160 229#define ACLK_DMAC 161 230#define ACLK_DCF 162 231#define ACLK_SPINLOCK 163 232#define ACLK_DECOM 164 233#define ACLK_PDCRYPTO 165 234#define ACLK_CRYPTO 166 235#define ACLK_PDVEPU 167 236#define ACLK_VENC 168 237#define ACLK_PDVDEC 169 238#define ACLK_PDJPEG 170 239#define ACLK_VDEC 171 240#define ACLK_JPEG 172 241#define ACLK_PDVO 173 242#define ACLK_RGA 174 243#define ACLK_VOP 175 244#define ACLK_IEP 176 245#define ACLK_PDVI_DIV 177 246#define ACLK_PDVI_NP5 178 247#define ACLK_PDVI 179 248#define ACLK_ISP 180 249#define ACLK_CIF 181 250#define ACLK_CIFLITE 182 251#define ACLK_PDISPP_DIV 183 252#define ACLK_PDISPP_NP5 184 253#define ACLK_PDISPP 185 254#define ACLK_ISPP 186 255#define ACLK_PDPHP 187 256#define ACLK_PDUSB 188 257#define ACLK_USBOTG 189 258#define ACLK_PDGMAC 190 259#define ACLK_GMAC 191 260#define ACLK_PDNPU_DIV 192 261#define ACLK_PDNPU_NP5 193 262#define ACLK_PDNPU 194 263#define ACLK_NPU 195 264 265/* hclk */ 266#define HCLK_PDCORE_NIU 200 267#define HCLK_PDUSB 201 268#define HCLK_PDCRYPTO 202 269#define HCLK_CRYPTO 203 270#define HCLK_PDAUDIO 204 271#define HCLK_I2S0 205 272#define HCLK_I2S1 206 273#define HCLK_I2S2 207 274#define HCLK_PDM 208 275#define HCLK_AUDPWM 209 276#define HCLK_PDVEPU 210 277#define HCLK_VENC 211 278#define HCLK_PDVDEC 212 279#define HCLK_PDJPEG 213 280#define HCLK_VDEC 214 281#define HCLK_JPEG 215 282#define HCLK_PDVO 216 283#define HCLK_RGA 217 284#define HCLK_VOP 218 285#define HCLK_IEP 219 286#define HCLK_PDVI 220 287#define HCLK_ISP 221 288#define HCLK_CIF 222 289#define HCLK_CIFLITE 223 290#define HCLK_PDISPP 224 291#define HCLK_ISPP 225 292#define HCLK_PDPHP 226 293#define HCLK_PDSDMMC 227 294#define HCLK_SDMMC 228 295#define HCLK_PDSDIO 229 296#define HCLK_SDIO 230 297#define HCLK_PDNVM 231 298#define HCLK_EMMC 232 299#define HCLK_NANDC 233 300#define HCLK_SFC 234 301#define HCLK_SFCXIP 235 302#define HCLK_PDBUS 236 303#define HCLK_USBHOST 237 304#define HCLK_USBHOST_ARB 238 305#define HCLK_PDNPU 239 306#define HCLK_NPU 240 307 308/* pclk */ 309#define PCLK_CPUPVTM 245 310#define PCLK_PDBUS 246 311#define PCLK_DCF 247 312#define PCLK_WDT 248 313#define PCLK_MAILBOX 249 314#define PCLK_UART0 250 315#define PCLK_UART2 251 316#define PCLK_UART3 252 317#define PCLK_UART4 253 318#define PCLK_UART5 254 319#define PCLK_I2C1 255 320#define PCLK_I2C3 256 321#define PCLK_I2C4 257 322#define PCLK_I2C5 258 323#define PCLK_SPI1 259 324#define PCLK_PWM2 261 325#define PCLK_GPIO1 262 326#define PCLK_GPIO2 263 327#define PCLK_GPIO3 264 328#define PCLK_GPIO4 265 329#define PCLK_SARADC 266 330#define PCLK_TIMER 267 331#define PCLK_DECOM 268 332#define PCLK_CAN 269 333#define PCLK_NPU_TSADC 270 334#define PCLK_CPU_TSADC 271 335#define PCLK_ACDCDIG 272 336#define PCLK_PDVO 273 337#define PCLK_DSIHOST 274 338#define PCLK_PDVI 275 339#define PCLK_CSIHOST 276 340#define PCLK_PDGMAC 277 341#define PCLK_GMAC 278 342#define PCLK_PDDDR 279 343#define PCLK_DDR_MON 280 344#define PCLK_PDNPU 281 345#define PCLK_NPUPVTM 282 346#define PCLK_PDTOP 283 347#define PCLK_TOPCRU 284 348#define PCLK_TOPGRF 285 349#define PCLK_CPUEMADET 286 350#define PCLK_DDRPHY 287 351#define PCLK_DSIPHY 289 352#define PCLK_CSIPHY0 290 353#define PCLK_CSIPHY1 291 354#define PCLK_USBPHY_HOST 292 355#define PCLK_USBPHY_OTG 293 356#define PCLK_OTP 294 357 358#define CLK_NR_CLKS (PCLK_OTP + 1) 359 360/* pmu soft-reset indices */ 361 362/* pmu_cru_softrst_con0 */ 363#define SRST_PDPMU_NIU_P 0 364#define SRST_PMU_SGRF_P 1 365#define SRST_PMU_SGRF_REMAP_P 2 366#define SRST_I2C0_P 3 367#define SRST_I2C0 4 368#define SRST_I2C2_P 7 369#define SRST_I2C2 8 370#define SRST_UART1_P 9 371#define SRST_UART1 10 372#define SRST_PWM0_P 11 373#define SRST_PWM0 12 374#define SRST_PWM1_P 13 375#define SRST_PWM1 14 376#define SRST_DDR_FAIL_SAFE 15 377 378/* pmu_cru_softrst_con1 */ 379#define SRST_GPIO0_P 17 380#define SRST_GPIO0_DB 18 381#define SRST_SPI0_P 19 382#define SRST_SPI0 20 383#define SRST_PMUGRF_P 21 384#define SRST_CHIPVEROTP_P 22 385#define SRST_PMUPVTM 24 386#define SRST_PMUPVTM_P 25 387#define SRST_PMUCRU_P 30 388 389/* soft-reset indices */ 390 391/* cru_softrst_con0 */ 392#define SRST_CORE0_PO 0 393#define SRST_CORE1_PO 1 394#define SRST_CORE2_PO 2 395#define SRST_CORE3_PO 3 396#define SRST_CORE0 4 397#define SRST_CORE1 5 398#define SRST_CORE2 6 399#define SRST_CORE3 7 400#define SRST_CORE0_DBG 8 401#define SRST_CORE1_DBG 9 402#define SRST_CORE2_DBG 10 403#define SRST_CORE3_DBG 11 404#define SRST_NL2 12 405#define SRST_CORE_NIU_A 13 406#define SRST_DBG_DAPLITE_P 14 407#define SRST_DAPLITE_P 15 408 409/* cru_softrst_con1 */ 410#define SRST_PDBUS_NIU1_A 16 411#define SRST_PDBUS_NIU1_H 17 412#define SRST_PDBUS_NIU1_P 18 413#define SRST_PDBUS_NIU2_A 19 414#define SRST_PDBUS_NIU2_H 20 415#define SRST_PDBUS_NIU3_A 21 416#define SRST_PDBUS_NIU3_H 22 417#define SRST_PDBUS_HOLD_NIU1_A 23 418#define SRST_DBG_NIU_P 24 419#define SRST_PDCORE_NIIU_H 25 420#define SRST_MUC_NIU 26 421#define SRST_DCF_A 29 422#define SRST_DCF_P 30 423#define SRST_SYSTEM_SRAM_A 31 424 425/* cru_softrst_con2 */ 426#define SRST_I2C1_P 32 427#define SRST_I2C1 33 428#define SRST_I2C3_P 34 429#define SRST_I2C3 35 430#define SRST_I2C4_P 36 431#define SRST_I2C4 37 432#define SRST_I2C5_P 38 433#define SRST_I2C5 39 434#define SRST_SPI1_P 40 435#define SRST_SPI1 41 436#define SRST_MCU_CORE 42 437#define SRST_PWM2_P 44 438#define SRST_PWM2 45 439#define SRST_SPINLOCK_A 46 440 441/* cru_softrst_con3 */ 442#define SRST_UART0_P 48 443#define SRST_UART0 49 444#define SRST_UART2_P 50 445#define SRST_UART2 51 446#define SRST_UART3_P 52 447#define SRST_UART3 53 448#define SRST_UART4_P 54 449#define SRST_UART4 55 450#define SRST_UART5_P 56 451#define SRST_UART5 57 452#define SRST_WDT_P 58 453#define SRST_SARADC_P 59 454#define SRST_GRF_P 61 455#define SRST_TIMER_P 62 456#define SRST_MAILBOX_P 63 457 458/* cru_softrst_con4 */ 459#define SRST_TIMER0 64 460#define SRST_TIMER1 65 461#define SRST_TIMER2 66 462#define SRST_TIMER3 67 463#define SRST_TIMER4 68 464#define SRST_TIMER5 69 465#define SRST_INTMUX_P 70 466#define SRST_GPIO1_P 72 467#define SRST_GPIO1_DB 73 468#define SRST_GPIO2_P 74 469#define SRST_GPIO2_DB 75 470#define SRST_GPIO3_P 76 471#define SRST_GPIO3_DB 77 472#define SRST_GPIO4_P 78 473#define SRST_GPIO4_DB 79 474 475/* cru_softrst_con5 */ 476#define SRST_CAN_P 80 477#define SRST_CAN 81 478#define SRST_DECOM_A 85 479#define SRST_DECOM_P 86 480#define SRST_DECOM_D 87 481#define SRST_PDCRYPTO_NIU_A 88 482#define SRST_PDCRYPTO_NIU_H 89 483#define SRST_CRYPTO_A 90 484#define SRST_CRYPTO_H 91 485#define SRST_CRYPTO_CORE 92 486#define SRST_CRYPTO_PKA 93 487#define SRST_SGRF_P 95 488 489/* cru_softrst_con6 */ 490#define SRST_PDAUDIO_NIU_H 96 491#define SRST_PDAUDIO_NIU_P 97 492#define SRST_I2S0_H 98 493#define SRST_I2S0_TX_M 99 494#define SRST_I2S0_RX_M 100 495#define SRST_I2S1_H 101 496#define SRST_I2S1_M 102 497#define SRST_I2S2_H 103 498#define SRST_I2S2_M 104 499#define SRST_PDM_H 105 500#define SRST_PDM_M 106 501#define SRST_AUDPWM_H 107 502#define SRST_AUDPWM 108 503#define SRST_ACDCDIG_P 109 504#define SRST_ACDCDIG 110 505 506/* cru_softrst_con7 */ 507#define SRST_PDVEPU_NIU_A 112 508#define SRST_PDVEPU_NIU_H 113 509#define SRST_VENC_A 114 510#define SRST_VENC_H 115 511#define SRST_VENC_CORE 116 512#define SRST_PDVDEC_NIU_A 117 513#define SRST_PDVDEC_NIU_H 118 514#define SRST_VDEC_A 119 515#define SRST_VDEC_H 120 516#define SRST_VDEC_CORE 121 517#define SRST_VDEC_CA 122 518#define SRST_VDEC_HEVC_CA 123 519#define SRST_PDJPEG_NIU_A 124 520#define SRST_PDJPEG_NIU_H 125 521#define SRST_JPEG_A 126 522#define SRST_JPEG_H 127 523 524/* cru_softrst_con8 */ 525#define SRST_PDVO_NIU_A 128 526#define SRST_PDVO_NIU_H 129 527#define SRST_PDVO_NIU_P 130 528#define SRST_RGA_A 131 529#define SRST_RGA_H 132 530#define SRST_RGA_CORE 133 531#define SRST_VOP_A 134 532#define SRST_VOP_H 135 533#define SRST_VOP_D 136 534#define SRST_TXBYTEHS_DSIHOST 137 535#define SRST_DSIHOST_P 138 536#define SRST_IEP_A 139 537#define SRST_IEP_H 140 538#define SRST_IEP_CORE 141 539#define SRST_ISP_RX_P 142 540 541/* cru_softrst_con9 */ 542#define SRST_PDVI_NIU_A 144 543#define SRST_PDVI_NIU_H 145 544#define SRST_PDVI_NIU_P 146 545#define SRST_ISP 147 546#define SRST_CIF_A 148 547#define SRST_CIF_H 149 548#define SRST_CIF_D 150 549#define SRST_CIF_P 151 550#define SRST_CIF_I 152 551#define SRST_CIF_RX_P 153 552#define SRST_PDISPP_NIU_A 154 553#define SRST_PDISPP_NIU_H 155 554#define SRST_ISPP_A 156 555#define SRST_ISPP_H 157 556#define SRST_ISPP 158 557#define SRST_CSIHOST_P 159 558 559/* cru_softrst_con10 */ 560#define SRST_PDPHPMID_NIU_A 160 561#define SRST_PDPHPMID_NIU_H 161 562#define SRST_PDNVM_NIU_H 163 563#define SRST_SDMMC_H 164 564#define SRST_SDIO_H 165 565#define SRST_EMMC_H 166 566#define SRST_SFC_H 167 567#define SRST_SFCXIP_H 168 568#define SRST_SFC 169 569#define SRST_NANDC_H 170 570#define SRST_NANDC 171 571#define SRST_PDSDMMC_H 173 572#define SRST_PDSDIO_H 174 573 574/* cru_softrst_con11 */ 575#define SRST_PDUSB_NIU_A 176 576#define SRST_PDUSB_NIU_H 177 577#define SRST_USBHOST_H 178 578#define SRST_USBHOST_ARB_H 179 579#define SRST_USBHOST_UTMI 180 580#define SRST_USBOTG_A 181 581#define SRST_USBPHY_OTG_P 182 582#define SRST_USBPHY_HOST_P 183 583#define SRST_USBPHYPOR_OTG 184 584#define SRST_USBPHYPOR_HOST 185 585#define SRST_PDGMAC_NIU_A 188 586#define SRST_PDGMAC_NIU_P 189 587#define SRST_GMAC_A 190 588 589/* cru_softrst_con12 */ 590#define SRST_DDR_DFICTL_P 193 591#define SRST_DDR_MON_P 194 592#define SRST_DDR_STANDBY_P 195 593#define SRST_DDR_GRF_P 196 594#define SRST_DDR_MSCH_P 197 595#define SRST_DDR_SPLIT_A 198 596#define SRST_DDR_MSCH 199 597#define SRST_DDR_DFICTL 202 598#define SRST_DDR_STANDBY 203 599#define SRST_NPUMCU_NIU 205 600#define SRST_DDRPHY_P 206 601#define SRST_DDRPHY 207 602 603/* cru_softrst_con13 */ 604#define SRST_PDNPU_NIU_A 208 605#define SRST_PDNPU_NIU_H 209 606#define SRST_PDNPU_NIU_P 210 607#define SRST_NPU_A 211 608#define SRST_NPU_H 212 609#define SRST_NPU 213 610#define SRST_NPUPVTM_P 214 611#define SRST_NPUPVTM 215 612#define SRST_NPU_TSADC_P 216 613#define SRST_NPU_TSADC 217 614#define SRST_NPU_TSADCPHY 218 615#define SRST_CIFLITE_A 220 616#define SRST_CIFLITE_H 221 617#define SRST_CIFLITE_D 222 618#define SRST_CIFLITE_RX_P 223 619 620/* cru_softrst_con14 */ 621#define SRST_TOPNIU_P 224 622#define SRST_TOPCRU_P 225 623#define SRST_TOPGRF_P 226 624#define SRST_CPUEMADET_P 227 625#define SRST_CSIPHY0_P 228 626#define SRST_CSIPHY1_P 229 627#define SRST_DSIPHY_P 230 628#define SRST_CPU_TSADC_P 232 629#define SRST_CPU_TSADC 233 630#define SRST_CPU_TSADCPHY 234 631#define SRST_CPUPVTM_P 235 632#define SRST_CPUPVTM 236 633 634#endif 635