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      1      1.1  jmcneill /*	$NetBSD: s3c2410.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.2  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * Copyright (c) 2013 Heiko Stuebner <heiko (at) sntech.de>
      6      1.1  jmcneill  *
      7      1.1  jmcneill  * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
      8      1.1  jmcneill  */
      9      1.1  jmcneill 
     10      1.1  jmcneill #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
     11      1.1  jmcneill #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
     12      1.1  jmcneill 
     13      1.1  jmcneill /*
     14      1.1  jmcneill  * Let each exported clock get a unique index, which is used on DT-enabled
     15      1.1  jmcneill  * platforms to lookup the clock from a clock specifier. These indices are
     16      1.1  jmcneill  * therefore considered an ABI and so must not be changed. This implies
     17      1.1  jmcneill  * that new clocks should be added either in free spaces between clock groups
     18      1.1  jmcneill  * or at the end.
     19      1.1  jmcneill  */
     20      1.1  jmcneill 
     21      1.1  jmcneill /* Core clocks. */
     22      1.1  jmcneill 
     23      1.1  jmcneill /* id 1 is reserved */
     24      1.1  jmcneill #define MPLL			2
     25      1.1  jmcneill #define UPLL			3
     26      1.1  jmcneill #define FCLK			4
     27      1.1  jmcneill #define HCLK			5
     28      1.1  jmcneill #define PCLK			6
     29      1.1  jmcneill #define UCLK			7
     30      1.1  jmcneill #define ARMCLK			8
     31      1.1  jmcneill 
     32      1.1  jmcneill /* pclk-gates */
     33      1.1  jmcneill #define PCLK_UART0		16
     34      1.1  jmcneill #define PCLK_UART1		17
     35      1.1  jmcneill #define PCLK_UART2		18
     36      1.1  jmcneill #define PCLK_I2C		19
     37      1.1  jmcneill #define PCLK_SDI		20
     38      1.1  jmcneill #define PCLK_SPI		21
     39      1.1  jmcneill #define PCLK_ADC		22
     40      1.1  jmcneill #define PCLK_AC97		23
     41      1.1  jmcneill #define PCLK_I2S		24
     42      1.1  jmcneill #define PCLK_PWM		25
     43      1.1  jmcneill #define PCLK_RTC		26
     44      1.1  jmcneill #define PCLK_GPIO		27
     45      1.1  jmcneill 
     46      1.1  jmcneill 
     47      1.1  jmcneill /* hclk-gates */
     48      1.1  jmcneill #define HCLK_LCD		32
     49      1.1  jmcneill #define HCLK_USBH		33
     50      1.1  jmcneill #define HCLK_USBD		34
     51      1.1  jmcneill #define HCLK_NAND		35
     52      1.1  jmcneill #define HCLK_CAM		36
     53      1.1  jmcneill 
     54      1.1  jmcneill 
     55      1.1  jmcneill #define CAMIF			40
     56      1.1  jmcneill 
     57      1.1  jmcneill 
     58      1.1  jmcneill /* Total number of clocks. */
     59      1.1  jmcneill #define NR_CLKS			(CAMIF + 1)
     60      1.1  jmcneill 
     61      1.1  jmcneill #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
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