samsung,s3c64xx-clock.h revision 1.1.1.1
1/* $NetBSD: samsung,s3c64xx-clock.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Device Tree binding constants for Samsung S3C64xx clock controller. 11*/ 12 13#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 14#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 15 16/* 17 * Let each exported clock get a unique index, which is used on DT-enabled 18 * platforms to lookup the clock from a clock specifier. These indices are 19 * therefore considered an ABI and so must not be changed. This implies 20 * that new clocks should be added either in free spaces between clock groups 21 * or at the end. 22 */ 23 24/* Core clocks. */ 25#define CLK27M 1 26#define CLK48M 2 27#define FOUT_APLL 3 28#define FOUT_MPLL 4 29#define FOUT_EPLL 5 30#define ARMCLK 6 31#define HCLKX2 7 32#define HCLK 8 33#define PCLK 9 34 35/* HCLK bus clocks. */ 36#define HCLK_3DSE 16 37#define HCLK_UHOST 17 38#define HCLK_SECUR 18 39#define HCLK_SDMA1 19 40#define HCLK_SDMA0 20 41#define HCLK_IROM 21 42#define HCLK_DDR1 22 43#define HCLK_MEM1 23 44#define HCLK_MEM0 24 45#define HCLK_USB 25 46#define HCLK_HSMMC2 26 47#define HCLK_HSMMC1 27 48#define HCLK_HSMMC0 28 49#define HCLK_MDP 29 50#define HCLK_DHOST 30 51#define HCLK_IHOST 31 52#define HCLK_DMA1 32 53#define HCLK_DMA0 33 54#define HCLK_JPEG 34 55#define HCLK_CAMIF 35 56#define HCLK_SCALER 36 57#define HCLK_2D 37 58#define HCLK_TV 38 59#define HCLK_POST0 39 60#define HCLK_ROT 40 61#define HCLK_LCD 41 62#define HCLK_TZIC 42 63#define HCLK_INTC 43 64#define HCLK_MFC 44 65#define HCLK_DDR0 45 66 67/* PCLK bus clocks. */ 68#define PCLK_IIC1 48 69#define PCLK_IIS2 49 70#define PCLK_SKEY 50 71#define PCLK_CHIPID 51 72#define PCLK_SPI1 52 73#define PCLK_SPI0 53 74#define PCLK_HSIRX 54 75#define PCLK_HSITX 55 76#define PCLK_GPIO 56 77#define PCLK_IIC0 57 78#define PCLK_IIS1 58 79#define PCLK_IIS0 59 80#define PCLK_AC97 60 81#define PCLK_TZPC 61 82#define PCLK_TSADC 62 83#define PCLK_KEYPAD 63 84#define PCLK_IRDA 64 85#define PCLK_PCM1 65 86#define PCLK_PCM0 66 87#define PCLK_PWM 67 88#define PCLK_RTC 68 89#define PCLK_WDT 69 90#define PCLK_UART3 70 91#define PCLK_UART2 71 92#define PCLK_UART1 72 93#define PCLK_UART0 73 94#define PCLK_MFC 74 95 96/* Special clocks. */ 97#define SCLK_UHOST 80 98#define SCLK_MMC2_48 81 99#define SCLK_MMC1_48 82 100#define SCLK_MMC0_48 83 101#define SCLK_MMC2 84 102#define SCLK_MMC1 85 103#define SCLK_MMC0 86 104#define SCLK_SPI1_48 87 105#define SCLK_SPI0_48 88 106#define SCLK_SPI1 89 107#define SCLK_SPI0 90 108#define SCLK_DAC27 91 109#define SCLK_TV27 92 110#define SCLK_SCALER27 93 111#define SCLK_SCALER 94 112#define SCLK_LCD27 95 113#define SCLK_LCD 96 114#define SCLK_FIMC 97 115#define SCLK_POST0_27 98 116#define SCLK_AUDIO2 99 117#define SCLK_POST0 100 118#define SCLK_AUDIO1 101 119#define SCLK_AUDIO0 102 120#define SCLK_SECUR 103 121#define SCLK_IRDA 104 122#define SCLK_UART 105 123#define SCLK_MFC 106 124#define SCLK_CAM 107 125#define SCLK_JPEG 108 126#define SCLK_ONENAND 109 127 128/* MEM0 bus clocks - S3C6410-specific. */ 129#define MEM0_CFCON 112 130#define MEM0_ONENAND1 113 131#define MEM0_ONENAND0 114 132#define MEM0_NFCON 115 133#define MEM0_SROM 116 134 135/* Muxes. */ 136#define MOUT_APLL 128 137#define MOUT_MPLL 129 138#define MOUT_EPLL 130 139#define MOUT_MFC 131 140#define MOUT_AUDIO0 132 141#define MOUT_AUDIO1 133 142#define MOUT_UART 134 143#define MOUT_SPI0 135 144#define MOUT_SPI1 136 145#define MOUT_MMC0 137 146#define MOUT_MMC1 138 147#define MOUT_MMC2 139 148#define MOUT_UHOST 140 149#define MOUT_IRDA 141 150#define MOUT_LCD 142 151#define MOUT_SCALER 143 152#define MOUT_DAC27 144 153#define MOUT_TV27 145 154#define MOUT_AUDIO2 146 155 156/* Dividers. */ 157#define DOUT_MPLL 160 158#define DOUT_SECUR 161 159#define DOUT_CAM 162 160#define DOUT_JPEG 163 161#define DOUT_MFC 164 162#define DOUT_MMC0 165 163#define DOUT_MMC1 166 164#define DOUT_MMC2 167 165#define DOUT_LCD 168 166#define DOUT_SCALER 169 167#define DOUT_UHOST 170 168#define DOUT_SPI0 171 169#define DOUT_SPI1 172 170#define DOUT_AUDIO0 173 171#define DOUT_AUDIO1 174 172#define DOUT_UART 175 173#define DOUT_IRDA 176 174#define DOUT_FIMC 177 175#define DOUT_AUDIO2 178 176 177/* Total number of clocks. */ 178#define NR_CLKS (DOUT_AUDIO2 + 1) 179 180#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ 181