1 1.1 jmcneill /* $NetBSD: stih407-clks.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * This header provides constants clk index STMicroelectronics 6 1.1 jmcneill * STiH407 SoC. 7 1.1 jmcneill */ 8 1.1 jmcneill #ifndef _DT_BINDINGS_CLK_STIH407 9 1.1 jmcneill #define _DT_BINDINGS_CLK_STIH407 10 1.1 jmcneill 11 1.1 jmcneill /* CLOCKGEN A0 */ 12 1.1 jmcneill #define CLK_IC_LMI0 0 13 1.1 jmcneill #define CLK_IC_LMI1 1 14 1.1 jmcneill 15 1.1 jmcneill /* CLOCKGEN C0 */ 16 1.1 jmcneill #define CLK_ICN_GPU 0 17 1.1 jmcneill #define CLK_FDMA 1 18 1.1 jmcneill #define CLK_NAND 2 19 1.1 jmcneill #define CLK_HVA 3 20 1.1 jmcneill #define CLK_PROC_STFE 4 21 1.1 jmcneill #define CLK_PROC_TP 5 22 1.1 jmcneill #define CLK_RX_ICN_DMU 6 23 1.1 jmcneill #define CLK_RX_ICN_DISP_0 6 24 1.1 jmcneill #define CLK_RX_ICN_DISP_1 6 25 1.1 jmcneill #define CLK_RX_ICN_HVA 7 26 1.1 jmcneill #define CLK_RX_ICN_TS 7 27 1.1 jmcneill #define CLK_ICN_CPU 8 28 1.1 jmcneill #define CLK_TX_ICN_DMU 9 29 1.1 jmcneill #define CLK_TX_ICN_HVA 9 30 1.1 jmcneill #define CLK_TX_ICN_TS 9 31 1.1 jmcneill #define CLK_ICN_COMPO 9 32 1.1 jmcneill #define CLK_MMC_0 10 33 1.1 jmcneill #define CLK_MMC_1 11 34 1.1 jmcneill #define CLK_JPEGDEC 12 35 1.1 jmcneill #define CLK_ICN_REG 13 36 1.1 jmcneill #define CLK_TRACE_A9 13 37 1.1 jmcneill #define CLK_PTI_STM 13 38 1.1 jmcneill #define CLK_EXT2F_A9 13 39 1.1 jmcneill #define CLK_IC_BDISP_0 14 40 1.1 jmcneill #define CLK_IC_BDISP_1 15 41 1.1 jmcneill #define CLK_PP_DMU 16 42 1.1 jmcneill #define CLK_VID_DMU 17 43 1.1 jmcneill #define CLK_DSS_LPC 18 44 1.1 jmcneill #define CLK_ST231_AUD_0 19 45 1.1 jmcneill #define CLK_ST231_GP_0 19 46 1.1 jmcneill #define CLK_ST231_GP_1 20 47 1.1 jmcneill #define CLK_ST231_DMU 21 48 1.1 jmcneill #define CLK_ICN_LMI 22 49 1.1 jmcneill #define CLK_TX_ICN_DISP_0 23 50 1.1 jmcneill #define CLK_TX_ICN_DISP_1 23 51 1.1 jmcneill #define CLK_ICN_SBC 24 52 1.1 jmcneill #define CLK_STFE_FRC2 25 53 1.1 jmcneill #define CLK_ETH_PHY 26 54 1.1 jmcneill #define CLK_ETH_REF_PHYCLK 27 55 1.1 jmcneill #define CLK_FLASH_PROMIP 28 56 1.1 jmcneill #define CLK_MAIN_DISP 29 57 1.1 jmcneill #define CLK_AUX_DISP 30 58 1.1 jmcneill #define CLK_COMPO_DVP 31 59 1.1 jmcneill 60 1.1 jmcneill /* CLOCKGEN D0 */ 61 1.1 jmcneill #define CLK_PCM_0 0 62 1.1 jmcneill #define CLK_PCM_1 1 63 1.1 jmcneill #define CLK_PCM_2 2 64 1.1 jmcneill #define CLK_SPDIFF 3 65 1.1 jmcneill 66 1.1 jmcneill /* CLOCKGEN D2 */ 67 1.1 jmcneill #define CLK_PIX_MAIN_DISP 0 68 1.1 jmcneill #define CLK_PIX_PIP 1 69 1.1 jmcneill #define CLK_PIX_GDP1 2 70 1.1 jmcneill #define CLK_PIX_GDP2 3 71 1.1 jmcneill #define CLK_PIX_GDP3 4 72 1.1 jmcneill #define CLK_PIX_GDP4 5 73 1.1 jmcneill #define CLK_PIX_AUX_DISP 6 74 1.1 jmcneill #define CLK_DENC 7 75 1.1 jmcneill #define CLK_PIX_HDDAC 8 76 1.1 jmcneill #define CLK_HDDAC 9 77 1.1 jmcneill #define CLK_SDDAC 10 78 1.1 jmcneill #define CLK_PIX_DVO 11 79 1.1 jmcneill #define CLK_DVO 12 80 1.1 jmcneill #define CLK_PIX_HDMI 13 81 1.1 jmcneill #define CLK_TMDS_HDMI 14 82 1.1 jmcneill #define CLK_REF_HDMIPHY 15 83 1.1 jmcneill 84 1.1 jmcneill /* CLOCKGEN D3 */ 85 1.1 jmcneill #define CLK_STFE_FRC1 0 86 1.1 jmcneill #define CLK_TSOUT_0 1 87 1.1 jmcneill #define CLK_TSOUT_1 2 88 1.1 jmcneill #define CLK_MCHI 3 89 1.1 jmcneill #define CLK_VSENS_COMPO 4 90 1.1 jmcneill #define CLK_FRC1_REMOTE 5 91 1.1 jmcneill #define CLK_LPC_0 6 92 1.1 jmcneill #define CLK_LPC_1 7 93 1.1 jmcneill #endif 94