1 /* $NetBSD: stih407-clks.h,v 1.1.1.1.4.2 2017/07/18 16:08:57 snj Exp $ */ 2 3 /* 4 * This header provides constants clk index STMicroelectronics 5 * STiH407 SoC. 6 */ 7 #ifndef _DT_BINDINGS_CLK_STIH407 8 #define _DT_BINDINGS_CLK_STIH407 9 10 /* CLOCKGEN A0 */ 11 #define CLK_IC_LMI0 0 12 #define CLK_IC_LMI1 1 13 14 /* CLOCKGEN C0 */ 15 #define CLK_ICN_GPU 0 16 #define CLK_FDMA 1 17 #define CLK_NAND 2 18 #define CLK_HVA 3 19 #define CLK_PROC_STFE 4 20 #define CLK_PROC_TP 5 21 #define CLK_RX_ICN_DMU 6 22 #define CLK_RX_ICN_DISP_0 6 23 #define CLK_RX_ICN_DISP_1 6 24 #define CLK_RX_ICN_HVA 7 25 #define CLK_RX_ICN_TS 7 26 #define CLK_ICN_CPU 8 27 #define CLK_TX_ICN_DMU 9 28 #define CLK_TX_ICN_HVA 9 29 #define CLK_TX_ICN_TS 9 30 #define CLK_ICN_COMPO 9 31 #define CLK_MMC_0 10 32 #define CLK_MMC_1 11 33 #define CLK_JPEGDEC 12 34 #define CLK_ICN_REG 13 35 #define CLK_TRACE_A9 13 36 #define CLK_PTI_STM 13 37 #define CLK_EXT2F_A9 13 38 #define CLK_IC_BDISP_0 14 39 #define CLK_IC_BDISP_1 15 40 #define CLK_PP_DMU 16 41 #define CLK_VID_DMU 17 42 #define CLK_DSS_LPC 18 43 #define CLK_ST231_AUD_0 19 44 #define CLK_ST231_GP_0 19 45 #define CLK_ST231_GP_1 20 46 #define CLK_ST231_DMU 21 47 #define CLK_ICN_LMI 22 48 #define CLK_TX_ICN_DISP_0 23 49 #define CLK_TX_ICN_DISP_1 23 50 #define CLK_ICN_SBC 24 51 #define CLK_STFE_FRC2 25 52 #define CLK_ETH_PHY 26 53 #define CLK_ETH_REF_PHYCLK 27 54 #define CLK_FLASH_PROMIP 28 55 #define CLK_MAIN_DISP 29 56 #define CLK_AUX_DISP 30 57 #define CLK_COMPO_DVP 31 58 59 /* CLOCKGEN D0 */ 60 #define CLK_PCM_0 0 61 #define CLK_PCM_1 1 62 #define CLK_PCM_2 2 63 #define CLK_SPDIFF 3 64 65 /* CLOCKGEN D2 */ 66 #define CLK_PIX_MAIN_DISP 0 67 #define CLK_PIX_PIP 1 68 #define CLK_PIX_GDP1 2 69 #define CLK_PIX_GDP2 3 70 #define CLK_PIX_GDP3 4 71 #define CLK_PIX_GDP4 5 72 #define CLK_PIX_AUX_DISP 6 73 #define CLK_DENC 7 74 #define CLK_PIX_HDDAC 8 75 #define CLK_HDDAC 9 76 #define CLK_SDDAC 10 77 #define CLK_PIX_DVO 11 78 #define CLK_DVO 12 79 #define CLK_PIX_HDMI 13 80 #define CLK_TMDS_HDMI 14 81 #define CLK_REF_HDMIPHY 15 82 83 /* CLOCKGEN D3 */ 84 #define CLK_STFE_FRC1 0 85 #define CLK_TSOUT_0 1 86 #define CLK_TSOUT_1 2 87 #define CLK_MCHI 3 88 #define CLK_VSENS_COMPO 4 89 #define CLK_FRC1_REMOTE 5 90 #define CLK_LPC_0 6 91 #define CLK_LPC_1 7 92 #endif 93