stm32mp13-clks.h revision 1.1.1.1
1/* $NetBSD: stm32mp13-clks.h,v 1.1.1.1 2026/01/18 05:21:41 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 4/* 5 * Copyright (C) STMicroelectronics 2020 - All Rights Reserved 6 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. 7 */ 8 9#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ 10#define _DT_BINDINGS_STM32MP13_CLKS_H_ 11 12/* OSCILLATOR clocks */ 13#define CK_HSE 0 14#define CK_CSI 1 15#define CK_LSI 2 16#define CK_LSE 3 17#define CK_HSI 4 18#define CK_HSE_DIV2 5 19 20/* PLL */ 21#define PLL1 6 22#define PLL2 7 23#define PLL3 8 24#define PLL4 9 25 26/* ODF */ 27#define PLL1_P 10 28#define PLL1_Q 11 29#define PLL1_R 12 30#define PLL2_P 13 31#define PLL2_Q 14 32#define PLL2_R 15 33#define PLL3_P 16 34#define PLL3_Q 17 35#define PLL3_R 18 36#define PLL4_P 19 37#define PLL4_Q 20 38#define PLL4_R 21 39 40#define PCLK1 22 41#define PCLK2 23 42#define PCLK3 24 43#define PCLK4 25 44#define PCLK5 26 45#define PCLK6 27 46 47/* SYSTEM CLOCK */ 48#define CK_PER 28 49#define CK_MPU 29 50#define CK_AXI 30 51#define CK_MLAHB 31 52 53/* BASE TIMER */ 54#define CK_TIMG1 32 55#define CK_TIMG2 33 56#define CK_TIMG3 34 57 58/* AUX */ 59#define RTC 35 60 61/* TRACE & DEBUG clocks */ 62#define CK_DBG 36 63#define CK_TRACE 37 64 65/* MCO clocks */ 66#define CK_MCO1 38 67#define CK_MCO2 39 68 69/* IP clocks */ 70#define SYSCFG 40 71#define VREF 41 72#define DTS 42 73#define PMBCTRL 43 74#define HDP 44 75#define IWDG2 45 76#define STGENRO 46 77#define USART1 47 78#define RTCAPB 48 79#define TZC 49 80#define TZPC 50 81#define IWDG1 51 82#define BSEC 52 83#define DMA1 53 84#define DMA2 54 85#define DMAMUX1 55 86#define DMAMUX2 56 87#define GPIOA 57 88#define GPIOB 58 89#define GPIOC 59 90#define GPIOD 60 91#define GPIOE 61 92#define GPIOF 62 93#define GPIOG 63 94#define GPIOH 64 95#define GPIOI 65 96#define CRYP1 66 97#define HASH1 67 98#define BKPSRAM 68 99#define MDMA 69 100#define CRC1 70 101#define USBH 71 102#define DMA3 72 103#define TSC 73 104#define PKA 74 105#define AXIMC 75 106#define MCE 76 107#define ETH1TX 77 108#define ETH2TX 78 109#define ETH1RX 79 110#define ETH2RX 80 111#define ETH1MAC 81 112#define ETH2MAC 82 113#define ETH1STP 83 114#define ETH2STP 84 115 116/* IP clocks with parents */ 117#define SDMMC1_K 85 118#define SDMMC2_K 86 119#define ADC1_K 87 120#define ADC2_K 88 121#define FMC_K 89 122#define QSPI_K 90 123#define RNG1_K 91 124#define USBPHY_K 92 125#define STGEN_K 93 126#define SPDIF_K 94 127#define SPI1_K 95 128#define SPI2_K 96 129#define SPI3_K 97 130#define SPI4_K 98 131#define SPI5_K 99 132#define I2C1_K 100 133#define I2C2_K 101 134#define I2C3_K 102 135#define I2C4_K 103 136#define I2C5_K 104 137#define TIM2_K 105 138#define TIM3_K 106 139#define TIM4_K 107 140#define TIM5_K 108 141#define TIM6_K 109 142#define TIM7_K 110 143#define TIM12_K 111 144#define TIM13_K 112 145#define TIM14_K 113 146#define TIM1_K 114 147#define TIM8_K 115 148#define TIM15_K 116 149#define TIM16_K 117 150#define TIM17_K 118 151#define LPTIM1_K 119 152#define LPTIM2_K 120 153#define LPTIM3_K 121 154#define LPTIM4_K 122 155#define LPTIM5_K 123 156#define USART1_K 124 157#define USART2_K 125 158#define USART3_K 126 159#define UART4_K 127 160#define UART5_K 128 161#define USART6_K 129 162#define UART7_K 130 163#define UART8_K 131 164#define DFSDM_K 132 165#define FDCAN_K 133 166#define SAI1_K 134 167#define SAI2_K 135 168#define ADFSDM_K 136 169#define USBO_K 137 170#define LTDC_PX 138 171#define ETH1CK_K 139 172#define ETH1PTP_K 140 173#define ETH2CK_K 141 174#define ETH2PTP_K 142 175#define DCMIPP_K 143 176#define SAES_K 144 177#define DTS_K 145 178 179/* DDR */ 180#define DDRC1 146 181#define DDRC1LP 147 182#define DDRC2 148 183#define DDRC2LP 149 184#define DDRPHYC 150 185#define DDRPHYCLP 151 186#define DDRCAPB 152 187#define DDRCAPBLP 153 188#define AXIDCG 154 189#define DDRPHYCAPB 155 190#define DDRPHYCAPBLP 156 191#define DDRPERFM 157 192 193#define ADC1 158 194#define ADC2 159 195#define SAI1 160 196#define SAI2 161 197 198#define STM32MP1_LAST_CLK 162 199 200/* SCMI clock identifiers */ 201#define CK_SCMI_HSE 0 202#define CK_SCMI_HSI 1 203#define CK_SCMI_CSI 2 204#define CK_SCMI_LSE 3 205#define CK_SCMI_LSI 4 206#define CK_SCMI_HSE_DIV2 5 207#define CK_SCMI_PLL2_Q 6 208#define CK_SCMI_PLL2_R 7 209#define CK_SCMI_PLL3_P 8 210#define CK_SCMI_PLL3_Q 9 211#define CK_SCMI_PLL3_R 10 212#define CK_SCMI_PLL4_P 11 213#define CK_SCMI_PLL4_Q 12 214#define CK_SCMI_PLL4_R 13 215#define CK_SCMI_MPU 14 216#define CK_SCMI_AXI 15 217#define CK_SCMI_MLAHB 16 218#define CK_SCMI_CKPER 17 219#define CK_SCMI_PCLK1 18 220#define CK_SCMI_PCLK2 19 221#define CK_SCMI_PCLK3 20 222#define CK_SCMI_PCLK4 21 223#define CK_SCMI_PCLK5 22 224#define CK_SCMI_PCLK6 23 225#define CK_SCMI_CKTIMG1 24 226#define CK_SCMI_CKTIMG2 25 227#define CK_SCMI_CKTIMG3 26 228#define CK_SCMI_RTC 27 229#define CK_SCMI_RTCAPB 28 230 231#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ 232