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      1  1.1  skrll /*	$NetBSD: sun20i-d1-ccu.h,v 1.1 2024/08/12 10:55:56 skrll Exp $	*/
      2  1.1  skrll 
      3  1.1  skrll /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
      4  1.1  skrll /*
      5  1.1  skrll  * Copyright (C) 2020 huangzhenwei (at) allwinnertech.com
      6  1.1  skrll  * Copyright (C) 2021 Samuel Holland <samuel (at) sholland.org>
      7  1.1  skrll  */
      8  1.1  skrll 
      9  1.1  skrll #ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
     10  1.1  skrll #define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
     11  1.1  skrll 
     12  1.1  skrll #define CLK_PLL_CPUX		0
     13  1.1  skrll #define CLK_PLL_DDR0		1
     14  1.1  skrll #define CLK_PLL_PERIPH0_4X	2
     15  1.1  skrll #define CLK_PLL_PERIPH0_2X	3
     16  1.1  skrll #define CLK_PLL_PERIPH0_800M	4
     17  1.1  skrll #define CLK_PLL_PERIPH0		5
     18  1.1  skrll #define CLK_PLL_PERIPH0_DIV3	6
     19  1.1  skrll #define CLK_PLL_VIDEO0_4X	7
     20  1.1  skrll #define CLK_PLL_VIDEO0_2X	8
     21  1.1  skrll #define CLK_PLL_VIDEO0		9
     22  1.1  skrll #define CLK_PLL_VIDEO1_4X	10
     23  1.1  skrll #define CLK_PLL_VIDEO1_2X	11
     24  1.1  skrll #define CLK_PLL_VIDEO1		12
     25  1.1  skrll #define CLK_PLL_VE		13
     26  1.1  skrll #define CLK_PLL_AUDIO0_4X	14
     27  1.1  skrll #define CLK_PLL_AUDIO0_2X	15
     28  1.1  skrll #define CLK_PLL_AUDIO0		16
     29  1.1  skrll #define CLK_PLL_AUDIO1		17
     30  1.1  skrll #define CLK_PLL_AUDIO1_DIV2	18
     31  1.1  skrll #define CLK_PLL_AUDIO1_DIV5	19
     32  1.1  skrll #define CLK_CPUX		20
     33  1.1  skrll #define CLK_CPUX_AXI		21
     34  1.1  skrll #define CLK_CPUX_APB		22
     35  1.1  skrll #define CLK_PSI_AHB		23
     36  1.1  skrll #define CLK_APB0		24
     37  1.1  skrll #define CLK_APB1		25
     38  1.1  skrll #define CLK_MBUS		26
     39  1.1  skrll #define CLK_DE			27
     40  1.1  skrll #define CLK_BUS_DE		28
     41  1.1  skrll #define CLK_DI			29
     42  1.1  skrll #define CLK_BUS_DI		30
     43  1.1  skrll #define CLK_G2D			31
     44  1.1  skrll #define CLK_BUS_G2D		32
     45  1.1  skrll #define CLK_CE			33
     46  1.1  skrll #define CLK_BUS_CE		34
     47  1.1  skrll #define CLK_VE			35
     48  1.1  skrll #define CLK_BUS_VE		36
     49  1.1  skrll #define CLK_BUS_DMA		37
     50  1.1  skrll #define CLK_BUS_MSGBOX0		38
     51  1.1  skrll #define CLK_BUS_MSGBOX1		39
     52  1.1  skrll #define CLK_BUS_MSGBOX2		40
     53  1.1  skrll #define CLK_BUS_SPINLOCK	41
     54  1.1  skrll #define CLK_BUS_HSTIMER		42
     55  1.1  skrll #define CLK_AVS			43
     56  1.1  skrll #define CLK_BUS_DBG		44
     57  1.1  skrll #define CLK_BUS_PWM		45
     58  1.1  skrll #define CLK_BUS_IOMMU		46
     59  1.1  skrll #define CLK_DRAM		47
     60  1.1  skrll #define CLK_MBUS_DMA		48
     61  1.1  skrll #define CLK_MBUS_VE		49
     62  1.1  skrll #define CLK_MBUS_CE		50
     63  1.1  skrll #define CLK_MBUS_TVIN		51
     64  1.1  skrll #define CLK_MBUS_CSI		52
     65  1.1  skrll #define CLK_MBUS_G2D		53
     66  1.1  skrll #define CLK_MBUS_RISCV		54
     67  1.1  skrll #define CLK_BUS_DRAM		55
     68  1.1  skrll #define CLK_MMC0		56
     69  1.1  skrll #define CLK_MMC1		57
     70  1.1  skrll #define CLK_MMC2		58
     71  1.1  skrll #define CLK_BUS_MMC0		59
     72  1.1  skrll #define CLK_BUS_MMC1		60
     73  1.1  skrll #define CLK_BUS_MMC2		61
     74  1.1  skrll #define CLK_BUS_UART0		62
     75  1.1  skrll #define CLK_BUS_UART1		63
     76  1.1  skrll #define CLK_BUS_UART2		64
     77  1.1  skrll #define CLK_BUS_UART3		65
     78  1.1  skrll #define CLK_BUS_UART4		66
     79  1.1  skrll #define CLK_BUS_UART5		67
     80  1.1  skrll #define CLK_BUS_I2C0		68
     81  1.1  skrll #define CLK_BUS_I2C1		69
     82  1.1  skrll #define CLK_BUS_I2C2		70
     83  1.1  skrll #define CLK_BUS_I2C3		71
     84  1.1  skrll #define CLK_SPI0		72
     85  1.1  skrll #define CLK_SPI1		73
     86  1.1  skrll #define CLK_BUS_SPI0		74
     87  1.1  skrll #define CLK_BUS_SPI1		75
     88  1.1  skrll #define CLK_EMAC_25M		76
     89  1.1  skrll #define CLK_BUS_EMAC		77
     90  1.1  skrll #define CLK_IR_TX		78
     91  1.1  skrll #define CLK_BUS_IR_TX		79
     92  1.1  skrll #define CLK_BUS_GPADC		80
     93  1.1  skrll #define CLK_BUS_THS		81
     94  1.1  skrll #define CLK_I2S0		82
     95  1.1  skrll #define CLK_I2S1		83
     96  1.1  skrll #define CLK_I2S2		84
     97  1.1  skrll #define CLK_I2S2_ASRC		85
     98  1.1  skrll #define CLK_BUS_I2S0		86
     99  1.1  skrll #define CLK_BUS_I2S1		87
    100  1.1  skrll #define CLK_BUS_I2S2		88
    101  1.1  skrll #define CLK_SPDIF_TX		89
    102  1.1  skrll #define CLK_SPDIF_RX		90
    103  1.1  skrll #define CLK_BUS_SPDIF		91
    104  1.1  skrll #define CLK_DMIC		92
    105  1.1  skrll #define CLK_BUS_DMIC		93
    106  1.1  skrll #define CLK_AUDIO_DAC		94
    107  1.1  skrll #define CLK_AUDIO_ADC		95
    108  1.1  skrll #define CLK_BUS_AUDIO		96
    109  1.1  skrll #define CLK_USB_OHCI0		97
    110  1.1  skrll #define CLK_USB_OHCI1		98
    111  1.1  skrll #define CLK_BUS_OHCI0		99
    112  1.1  skrll #define CLK_BUS_OHCI1		100
    113  1.1  skrll #define CLK_BUS_EHCI0		101
    114  1.1  skrll #define CLK_BUS_EHCI1		102
    115  1.1  skrll #define CLK_BUS_OTG		103
    116  1.1  skrll #define CLK_BUS_LRADC		104
    117  1.1  skrll #define CLK_BUS_DPSS_TOP	105
    118  1.1  skrll #define CLK_HDMI_24M		106
    119  1.1  skrll #define CLK_HDMI_CEC_32K	107
    120  1.1  skrll #define CLK_HDMI_CEC		108
    121  1.1  skrll #define CLK_BUS_HDMI		109
    122  1.1  skrll #define CLK_MIPI_DSI		110
    123  1.1  skrll #define CLK_BUS_MIPI_DSI	111
    124  1.1  skrll #define CLK_TCON_LCD0		112
    125  1.1  skrll #define CLK_BUS_TCON_LCD0	113
    126  1.1  skrll #define CLK_TCON_TV		114
    127  1.1  skrll #define CLK_BUS_TCON_TV		115
    128  1.1  skrll #define CLK_TVE			116
    129  1.1  skrll #define CLK_BUS_TVE_TOP		117
    130  1.1  skrll #define CLK_BUS_TVE		118
    131  1.1  skrll #define CLK_TVD			119
    132  1.1  skrll #define CLK_BUS_TVD_TOP		120
    133  1.1  skrll #define CLK_BUS_TVD		121
    134  1.1  skrll #define CLK_LEDC		122
    135  1.1  skrll #define CLK_BUS_LEDC		123
    136  1.1  skrll #define CLK_CSI_TOP		124
    137  1.1  skrll #define CLK_CSI_MCLK		125
    138  1.1  skrll #define CLK_BUS_CSI		126
    139  1.1  skrll #define CLK_TPADC		127
    140  1.1  skrll #define CLK_BUS_TPADC		128
    141  1.1  skrll #define CLK_BUS_TZMA		129
    142  1.1  skrll #define CLK_DSP			130
    143  1.1  skrll #define CLK_BUS_DSP_CFG		131
    144  1.1  skrll #define CLK_RISCV		132
    145  1.1  skrll #define CLK_RISCV_AXI		133
    146  1.1  skrll #define CLK_BUS_RISCV_CFG	134
    147  1.1  skrll #define CLK_FANOUT_24M		135
    148  1.1  skrll #define CLK_FANOUT_12M		136
    149  1.1  skrll #define CLK_FANOUT_16M		137
    150  1.1  skrll #define CLK_FANOUT_25M		138
    151  1.1  skrll #define CLK_FANOUT_32K		139
    152  1.1  skrll #define CLK_FANOUT_27M		140
    153  1.1  skrll #define CLK_FANOUT_PCLK		141
    154  1.1  skrll #define CLK_FANOUT0		142
    155  1.1  skrll #define CLK_FANOUT1		143
    156  1.1  skrll #define CLK_FANOUT2		144
    157  1.1  skrll #define CLK_BUS_CAN0		145
    158  1.1  skrll #define CLK_BUS_CAN1		146
    159  1.1  skrll 
    160  1.1  skrll #endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
    161