tegra186-clock.h revision 1.1.1.1.6.2
1 /* $NetBSD: tegra186-clock.h,v 1.1.1.1.6.2 2017/08/28 17:53:01 skrll Exp $ */ 2 3 /** @file */ 4 5 #ifndef _MACH_T186_CLK_T186_H 6 #define _MACH_T186_CLK_T186_H 7 8 /** 9 * @defgroup clock_ids Clock Identifiers 10 * @{ 11 * @defgroup extern_input external input clocks 12 * @{ 13 * @def TEGRA186_CLK_OSC 14 * @def TEGRA186_CLK_CLK_32K 15 * @def TEGRA186_CLK_DTV_INPUT 16 * @def TEGRA186_CLK_SOR0_PAD_CLKOUT 17 * @def TEGRA186_CLK_SOR1_PAD_CLKOUT 18 * @def TEGRA186_CLK_I2S1_SYNC_INPUT 19 * @def TEGRA186_CLK_I2S2_SYNC_INPUT 20 * @def TEGRA186_CLK_I2S3_SYNC_INPUT 21 * @def TEGRA186_CLK_I2S4_SYNC_INPUT 22 * @def TEGRA186_CLK_I2S5_SYNC_INPUT 23 * @def TEGRA186_CLK_I2S6_SYNC_INPUT 24 * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT 25 * @} 26 * 27 * @defgroup extern_output external output clocks 28 * @{ 29 * @def TEGRA186_CLK_EXTPERIPH1 30 * @def TEGRA186_CLK_EXTPERIPH2 31 * @def TEGRA186_CLK_EXTPERIPH3 32 * @def TEGRA186_CLK_EXTPERIPH4 33 * @} 34 * 35 * @defgroup display_clks display related clocks 36 * @{ 37 * @def TEGRA186_CLK_CEC 38 * @def TEGRA186_CLK_DSIC 39 * @def TEGRA186_CLK_DSIC_LP 40 * @def TEGRA186_CLK_DSID 41 * @def TEGRA186_CLK_DSID_LP 42 * @def TEGRA186_CLK_DPAUX1 43 * @def TEGRA186_CLK_DPAUX 44 * @def TEGRA186_CLK_HDA2HDMICODEC 45 * @def TEGRA186_CLK_NVDISPLAY_DISP 46 * @def TEGRA186_CLK_NVDISPLAY_DSC 47 * @def TEGRA186_CLK_NVDISPLAY_P0 48 * @def TEGRA186_CLK_NVDISPLAY_P1 49 * @def TEGRA186_CLK_NVDISPLAY_P2 50 * @def TEGRA186_CLK_NVDISPLAYHUB 51 * @def TEGRA186_CLK_SOR_SAFE 52 * @def TEGRA186_CLK_SOR0 53 * @def TEGRA186_CLK_SOR0_OUT 54 * @def TEGRA186_CLK_SOR1 55 * @def TEGRA186_CLK_SOR1_OUT 56 * @def TEGRA186_CLK_DSI 57 * @def TEGRA186_CLK_MIPI_CAL 58 * @def TEGRA186_CLK_DSIA_LP 59 * @def TEGRA186_CLK_DSIB 60 * @def TEGRA186_CLK_DSIB_LP 61 * @} 62 * 63 * @defgroup camera_clks camera related clocks 64 * @{ 65 * @def TEGRA186_CLK_NVCSI 66 * @def TEGRA186_CLK_NVCSILP 67 * @def TEGRA186_CLK_VI 68 * @} 69 * 70 * @defgroup audio_clks audio related clocks 71 * @{ 72 * @def TEGRA186_CLK_ACLK 73 * @def TEGRA186_CLK_ADSP 74 * @def TEGRA186_CLK_ADSPNEON 75 * @def TEGRA186_CLK_AHUB 76 * @def TEGRA186_CLK_APE 77 * @def TEGRA186_CLK_APB2APE 78 * @def TEGRA186_CLK_AUD_MCLK 79 * @def TEGRA186_CLK_DMIC1 80 * @def TEGRA186_CLK_DMIC2 81 * @def TEGRA186_CLK_DMIC3 82 * @def TEGRA186_CLK_DMIC4 83 * @def TEGRA186_CLK_DSPK1 84 * @def TEGRA186_CLK_DSPK2 85 * @def TEGRA186_CLK_HDA 86 * @def TEGRA186_CLK_HDA2CODEC_2X 87 * @def TEGRA186_CLK_I2S1 88 * @def TEGRA186_CLK_I2S2 89 * @def TEGRA186_CLK_I2S3 90 * @def TEGRA186_CLK_I2S4 91 * @def TEGRA186_CLK_I2S5 92 * @def TEGRA186_CLK_I2S6 93 * @def TEGRA186_CLK_MAUD 94 * @def TEGRA186_CLK_PLL_A_OUT0 95 * @def TEGRA186_CLK_SPDIF_DOUBLER 96 * @def TEGRA186_CLK_SPDIF_IN 97 * @def TEGRA186_CLK_SPDIF_OUT 98 * @def TEGRA186_CLK_SYNC_DMIC1 99 * @def TEGRA186_CLK_SYNC_DMIC2 100 * @def TEGRA186_CLK_SYNC_DMIC3 101 * @def TEGRA186_CLK_SYNC_DMIC4 102 * @def TEGRA186_CLK_SYNC_DMIC5 103 * @def TEGRA186_CLK_SYNC_DSPK1 104 * @def TEGRA186_CLK_SYNC_DSPK2 105 * @def TEGRA186_CLK_SYNC_I2S1 106 * @def TEGRA186_CLK_SYNC_I2S2 107 * @def TEGRA186_CLK_SYNC_I2S3 108 * @def TEGRA186_CLK_SYNC_I2S4 109 * @def TEGRA186_CLK_SYNC_I2S5 110 * @def TEGRA186_CLK_SYNC_I2S6 111 * @def TEGRA186_CLK_SYNC_SPDIF 112 * @} 113 * 114 * @defgroup uart_clks UART clocks 115 * @{ 116 * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL 117 * @def TEGRA186_CLK_UARTA 118 * @def TEGRA186_CLK_UARTB 119 * @def TEGRA186_CLK_UARTC 120 * @def TEGRA186_CLK_UARTD 121 * @def TEGRA186_CLK_UARTE 122 * @def TEGRA186_CLK_UARTF 123 * @def TEGRA186_CLK_UARTG 124 * @def TEGRA186_CLK_UART_FST_MIPI_CAL 125 * @} 126 * 127 * @defgroup i2c_clks I2C clocks 128 * @{ 129 * @def TEGRA186_CLK_AON_I2C_SLOW 130 * @def TEGRA186_CLK_I2C1 131 * @def TEGRA186_CLK_I2C2 132 * @def TEGRA186_CLK_I2C3 133 * @def TEGRA186_CLK_I2C4 134 * @def TEGRA186_CLK_I2C5 135 * @def TEGRA186_CLK_I2C6 136 * @def TEGRA186_CLK_I2C8 137 * @def TEGRA186_CLK_I2C9 138 * @def TEGRA186_CLK_I2C1 139 * @def TEGRA186_CLK_I2C12 140 * @def TEGRA186_CLK_I2C13 141 * @def TEGRA186_CLK_I2C14 142 * @def TEGRA186_CLK_I2C_SLOW 143 * @def TEGRA186_CLK_VI_I2C 144 * @} 145 * 146 * @defgroup spi_clks SPI clocks 147 * @{ 148 * @def TEGRA186_CLK_SPI1 149 * @def TEGRA186_CLK_SPI2 150 * @def TEGRA186_CLK_SPI3 151 * @def TEGRA186_CLK_SPI4 152 * @} 153 * 154 * @defgroup storage storage related clocks 155 * @{ 156 * @def TEGRA186_CLK_SATA 157 * @def TEGRA186_CLK_SATA_OOB 158 * @def TEGRA186_CLK_SATA_IOBIST 159 * @def TEGRA186_CLK_SDMMC_LEGACY_TM 160 * @def TEGRA186_CLK_SDMMC1 161 * @def TEGRA186_CLK_SDMMC2 162 * @def TEGRA186_CLK_SDMMC3 163 * @def TEGRA186_CLK_SDMMC4 164 * @def TEGRA186_CLK_QSPI 165 * @def TEGRA186_CLK_QSPI_OUT 166 * @def TEGRA186_CLK_UFSDEV_REF 167 * @def TEGRA186_CLK_UFSHC 168 * @} 169 * 170 * @defgroup pwm_clks PWM clocks 171 * @{ 172 * @def TEGRA186_CLK_PWM1 173 * @def TEGRA186_CLK_PWM2 174 * @def TEGRA186_CLK_PWM3 175 * @def TEGRA186_CLK_PWM4 176 * @def TEGRA186_CLK_PWM5 177 * @def TEGRA186_CLK_PWM6 178 * @def TEGRA186_CLK_PWM7 179 * @def TEGRA186_CLK_PWM8 180 * @} 181 * 182 * @defgroup plls PLLs and related clocks 183 * @{ 184 * @def TEGRA186_CLK_PLLREFE_OUT_GATED 185 * @def TEGRA186_CLK_PLLREFE_OUT1 186 * @def TEGRA186_CLK_PLLD_OUT1 187 * @def TEGRA186_CLK_PLLP_OUT0 188 * @def TEGRA186_CLK_PLLP_OUT5 189 * @def TEGRA186_CLK_PLLA 190 * @def TEGRA186_CLK_PLLE_PWRSEQ 191 * @def TEGRA186_CLK_PLLA_OUT1 192 * @def TEGRA186_CLK_PLLREFE_REF 193 * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ 194 * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ 195 * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 196 * @def TEGRA186_CLK_PLLREFE_PEX 197 * @def TEGRA186_CLK_PLLREFE_IDDQ 198 * @def TEGRA186_CLK_PLLC_OUT_AON 199 * @def TEGRA186_CLK_PLLC_OUT_ISP 200 * @def TEGRA186_CLK_PLLC_OUT_VE 201 * @def TEGRA186_CLK_PLLC4_OUT 202 * @def TEGRA186_CLK_PLLREFE_OUT 203 * @def TEGRA186_CLK_PLLREFE_PLL_REF 204 * @def TEGRA186_CLK_PLLE 205 * @def TEGRA186_CLK_PLLC 206 * @def TEGRA186_CLK_PLLP 207 * @def TEGRA186_CLK_PLLD 208 * @def TEGRA186_CLK_PLLD2 209 * @def TEGRA186_CLK_PLLREFE_VCO 210 * @def TEGRA186_CLK_PLLC2 211 * @def TEGRA186_CLK_PLLC3 212 * @def TEGRA186_CLK_PLLDP 213 * @def TEGRA186_CLK_PLLC4_VCO 214 * @def TEGRA186_CLK_PLLA1 215 * @def TEGRA186_CLK_PLLNVCSI 216 * @def TEGRA186_CLK_PLLDISPHUB 217 * @def TEGRA186_CLK_PLLD3 218 * @def TEGRA186_CLK_PLLBPMPCAM 219 * @def TEGRA186_CLK_PLLAON 220 * @def TEGRA186_CLK_PLLU 221 * @def TEGRA186_CLK_PLLC4_VCO_DIV2 222 * @def TEGRA186_CLK_PLL_REF 223 * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 224 * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ 225 * @def TEGRA186_CLK_PLL_U_48M 226 * @def TEGRA186_CLK_PLL_U_480M 227 * @def TEGRA186_CLK_PLLC4_OUT0 228 * @def TEGRA186_CLK_PLLC4_OUT1 229 * @def TEGRA186_CLK_PLLC4_OUT2 230 * @def TEGRA186_CLK_PLLC4_OUT_MUX 231 * @def TEGRA186_CLK_DFLLDISP_DIV 232 * @def TEGRA186_CLK_PLLDISPHUB_DIV 233 * @def TEGRA186_CLK_PLLP_DIV8 234 * @} 235 * 236 * @defgroup nafll_clks NAFLL clock sources 237 * @{ 238 * @def TEGRA186_CLK_NAFLL_AXI_CBB 239 * @def TEGRA186_CLK_NAFLL_BCPU 240 * @def TEGRA186_CLK_NAFLL_BPMP 241 * @def TEGRA186_CLK_NAFLL_DISP 242 * @def TEGRA186_CLK_NAFLL_GPU 243 * @def TEGRA186_CLK_NAFLL_ISP 244 * @def TEGRA186_CLK_NAFLL_MCPU 245 * @def TEGRA186_CLK_NAFLL_NVDEC 246 * @def TEGRA186_CLK_NAFLL_NVENC 247 * @def TEGRA186_CLK_NAFLL_NVJPG 248 * @def TEGRA186_CLK_NAFLL_SCE 249 * @def TEGRA186_CLK_NAFLL_SE 250 * @def TEGRA186_CLK_NAFLL_TSEC 251 * @def TEGRA186_CLK_NAFLL_TSECB 252 * @def TEGRA186_CLK_NAFLL_VI 253 * @def TEGRA186_CLK_NAFLL_VIC 254 * @} 255 * 256 * @defgroup mphy MPHY related clocks 257 * @{ 258 * @def TEGRA186_CLK_MPHY_L0_RX_SYMB 259 * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT 260 * @def TEGRA186_CLK_MPHY_L0_TX_SYMB 261 * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 262 * @def TEGRA186_CLK_MPHY_L0_RX_ANA 263 * @def TEGRA186_CLK_MPHY_L1_RX_ANA 264 * @def TEGRA186_CLK_MPHY_IOBIST 265 * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF 266 * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED 267 * @} 268 * 269 * @defgroup eavb EAVB related clocks 270 * @{ 271 * @def TEGRA186_CLK_EQOS_AXI 272 * @def TEGRA186_CLK_EQOS_PTP_REF 273 * @def TEGRA186_CLK_EQOS_RX 274 * @def TEGRA186_CLK_EQOS_RX_INPUT 275 * @def TEGRA186_CLK_EQOS_TX 276 * @} 277 * 278 * @defgroup usb USB related clocks 279 * @{ 280 * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT 281 * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT 282 * @def TEGRA186_CLK_HSIC_TRK 283 * @def TEGRA186_CLK_USB2_TRK 284 * @def TEGRA186_CLK_USB2_HSIC_TRK 285 * @def TEGRA186_CLK_XUSB_CORE_SS 286 * @def TEGRA186_CLK_XUSB_CORE_DEV 287 * @def TEGRA186_CLK_XUSB_FALCON 288 * @def TEGRA186_CLK_XUSB_FS 289 * @def TEGRA186_CLK_XUSB 290 * @def TEGRA186_CLK_XUSB_DEV 291 * @def TEGRA186_CLK_XUSB_HOST 292 * @def TEGRA186_CLK_XUSB_SS 293 * @} 294 * 295 * @defgroup bigblock compute block related clocks 296 * @{ 297 * @def TEGRA186_CLK_GPCCLK 298 * @def TEGRA186_CLK_GPC2CLK 299 * @def TEGRA186_CLK_GPU 300 * @def TEGRA186_CLK_HOST1X 301 * @def TEGRA186_CLK_ISP 302 * @def TEGRA186_CLK_NVDEC 303 * @def TEGRA186_CLK_NVENC 304 * @def TEGRA186_CLK_NVJPG 305 * @def TEGRA186_CLK_SE 306 * @def TEGRA186_CLK_TSEC 307 * @def TEGRA186_CLK_TSECB 308 * @def TEGRA186_CLK_VIC 309 * @} 310 * 311 * @defgroup can CAN bus related clocks 312 * @{ 313 * @def TEGRA186_CLK_CAN1 314 * @def TEGRA186_CLK_CAN1_HOST 315 * @def TEGRA186_CLK_CAN2 316 * @def TEGRA186_CLK_CAN2_HOST 317 * @} 318 * 319 * @defgroup system basic system clocks 320 * @{ 321 * @def TEGRA186_CLK_ACTMON 322 * @def TEGRA186_CLK_AON_APB 323 * @def TEGRA186_CLK_AON_CPU_NIC 324 * @def TEGRA186_CLK_AON_NIC 325 * @def TEGRA186_CLK_AXI_CBB 326 * @def TEGRA186_CLK_BPMP_APB 327 * @def TEGRA186_CLK_BPMP_CPU_NIC 328 * @def TEGRA186_CLK_BPMP_NIC_RATE 329 * @def TEGRA186_CLK_CLK_M 330 * @def TEGRA186_CLK_EMC 331 * @def TEGRA186_CLK_MSS_ENCRYPT 332 * @def TEGRA186_CLK_SCE_APB 333 * @def TEGRA186_CLK_SCE_CPU_NIC 334 * @def TEGRA186_CLK_SCE_NIC 335 * @def TEGRA186_CLK_TSC 336 * @} 337 * 338 * @defgroup pcie_clks PCIe related clocks 339 * @{ 340 * @def TEGRA186_CLK_AFI 341 * @def TEGRA186_CLK_PCIE 342 * @def TEGRA186_CLK_PCIE2_IOBIST 343 * @def TEGRA186_CLK_PCIERX0 344 * @def TEGRA186_CLK_PCIERX1 345 * @def TEGRA186_CLK_PCIERX2 346 * @def TEGRA186_CLK_PCIERX3 347 * @def TEGRA186_CLK_PCIERX4 348 * @} 349 */ 350 351 /** @brief output of gate CLK_ENB_FUSE */ 352 #define TEGRA186_CLK_FUSE 0 353 /** 354 * @brief It's not what you think 355 * @details output of gate CLK_ENB_GPU. This output connects to the GPU 356 * pwrclk. @warning: This is almost certainly not the clock you think 357 * it is. If you're looking for the clock of the graphics engine, see 358 * TEGRA186_GPCCLK 359 */ 360 #define TEGRA186_CLK_GPU 1 361 /** @brief output of gate CLK_ENB_PCIE */ 362 #define TEGRA186_CLK_PCIE 3 363 /** @brief output of the divider IPFS_CLK_DIVISOR */ 364 #define TEGRA186_CLK_AFI 4 365 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */ 366 #define TEGRA186_CLK_PCIE2_IOBIST 5 367 /** @brief output of gate CLK_ENB_PCIERX0*/ 368 #define TEGRA186_CLK_PCIERX0 6 369 /** @brief output of gate CLK_ENB_PCIERX1*/ 370 #define TEGRA186_CLK_PCIERX1 7 371 /** @brief output of gate CLK_ENB_PCIERX2*/ 372 #define TEGRA186_CLK_PCIERX2 8 373 /** @brief output of gate CLK_ENB_PCIERX3*/ 374 #define TEGRA186_CLK_PCIERX3 9 375 /** @brief output of gate CLK_ENB_PCIERX4*/ 376 #define TEGRA186_CLK_PCIERX4 10 377 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ 378 #define TEGRA186_CLK_PLLC_OUT_ISP 11 379 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ 380 #define TEGRA186_CLK_PLLC_OUT_VE 12 381 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ 382 #define TEGRA186_CLK_PLLC_OUT_AON 13 383 /** @brief output of gate CLK_ENB_SOR_SAFE */ 384 #define TEGRA186_CLK_SOR_SAFE 39 385 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 386 #define TEGRA186_CLK_I2S2 42 387 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 388 #define TEGRA186_CLK_I2S3 43 389 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ 390 #define TEGRA186_CLK_SPDIF_IN 44 391 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ 392 #define TEGRA186_CLK_SPDIF_DOUBLER 45 393 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ 394 #define TEGRA186_CLK_SPI3 46 395 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ 396 #define TEGRA186_CLK_I2C1 47 397 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ 398 #define TEGRA186_CLK_I2C5 48 399 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 400 #define TEGRA186_CLK_SPI1 49 401 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 402 #define TEGRA186_CLK_ISP 50 403 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 404 #define TEGRA186_CLK_VI 51 405 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 406 #define TEGRA186_CLK_SDMMC1 52 407 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ 408 #define TEGRA186_CLK_SDMMC2 53 409 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 410 #define TEGRA186_CLK_SDMMC4 54 411 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 412 #define TEGRA186_CLK_UARTA 55 413 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 414 #define TEGRA186_CLK_UARTB 56 415 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 416 #define TEGRA186_CLK_HOST1X 57 417 /** 418 * @brief controls the EMC clock frequency. 419 * @details Doing a clk_set_rate on this clock will select the 420 * appropriate clock source, program the source rate and execute a 421 * specific sequence to switch to the new clock source for both memory 422 * controllers. This can be used to control the balance between memory 423 * throughput and memory controller power. 424 */ 425 #define TEGRA186_CLK_EMC 58 426 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 427 #define TEGRA186_CLK_EXTPERIPH4 73 428 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 429 #define TEGRA186_CLK_SPI4 74 430 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 431 #define TEGRA186_CLK_I2C3 75 432 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ 433 #define TEGRA186_CLK_SDMMC3 76 434 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 435 #define TEGRA186_CLK_UARTD 77 436 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 437 #define TEGRA186_CLK_I2S1 79 438 /** output of gate CLK_ENB_DTV */ 439 #define TEGRA186_CLK_DTV 80 440 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 441 #define TEGRA186_CLK_TSEC 81 442 /** @brief output of gate CLK_ENB_DP2 */ 443 #define TEGRA186_CLK_DP2 82 444 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 445 #define TEGRA186_CLK_I2S4 84 446 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 447 #define TEGRA186_CLK_I2S5 85 448 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 449 #define TEGRA186_CLK_I2C4 86 450 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 451 #define TEGRA186_CLK_AHUB 87 452 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 453 #define TEGRA186_CLK_HDA2CODEC_2X 88 454 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 455 #define TEGRA186_CLK_EXTPERIPH1 89 456 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 457 #define TEGRA186_CLK_EXTPERIPH2 90 458 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 459 #define TEGRA186_CLK_EXTPERIPH3 91 460 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 461 #define TEGRA186_CLK_I2C_SLOW 92 462 /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 463 #define TEGRA186_CLK_SOR1 93 464 /** @brief output of gate CLK_ENB_CEC */ 465 #define TEGRA186_CLK_CEC 94 466 /** @brief output of gate CLK_ENB_DPAUX1 */ 467 #define TEGRA186_CLK_DPAUX1 95 468 /** @brief output of gate CLK_ENB_DPAUX */ 469 #define TEGRA186_CLK_DPAUX 96 470 /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 471 #define TEGRA186_CLK_SOR0 97 472 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */ 473 #define TEGRA186_CLK_HDA2HDMICODEC 98 474 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ 475 #define TEGRA186_CLK_SATA 99 476 /** @brief output of gate CLK_ENB_SATA_OOB */ 477 #define TEGRA186_CLK_SATA_OOB 100 478 /** @brief output of gate CLK_ENB_SATA_IOBIST */ 479 #define TEGRA186_CLK_SATA_IOBIST 101 480 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ 481 #define TEGRA186_CLK_HDA 102 482 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ 483 #define TEGRA186_CLK_SE 103 484 /** @brief output of gate CLK_ENB_APB2APE */ 485 #define TEGRA186_CLK_APB2APE 104 486 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 487 #define TEGRA186_CLK_APE 105 488 /** @brief output of gate CLK_ENB_IQC1 */ 489 #define TEGRA186_CLK_IQC1 106 490 /** @brief output of gate CLK_ENB_IQC2 */ 491 #define TEGRA186_CLK_IQC2 107 492 /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ 493 #define TEGRA186_CLK_PLLREFE_OUT 108 494 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ 495 #define TEGRA186_CLK_PLLREFE_PLL_REF 109 496 /** @brief output of gate CLK_ENB_PLLC4_OUT */ 497 #define TEGRA186_CLK_PLLC4_OUT 110 498 /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ 499 #define TEGRA186_CLK_XUSB 111 500 /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ 501 #define TEGRA186_CLK_XUSB_DEV 112 502 /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ 503 #define TEGRA186_CLK_XUSB_HOST 113 504 /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ 505 #define TEGRA186_CLK_XUSB_SS 114 506 /** @brief output of gate CLK_ENB_DSI */ 507 #define TEGRA186_CLK_DSI 115 508 /** @brief output of gate CLK_ENB_MIPI_CAL */ 509 #define TEGRA186_CLK_MIPI_CAL 116 510 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ 511 #define TEGRA186_CLK_DSIA_LP 117 512 /** @brief output of gate CLK_ENB_DSIB */ 513 #define TEGRA186_CLK_DSIB 118 514 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ 515 #define TEGRA186_CLK_DSIB_LP 119 516 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 517 #define TEGRA186_CLK_DMIC1 122 518 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 519 #define TEGRA186_CLK_DMIC2 123 520 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 521 #define TEGRA186_CLK_AUD_MCLK 124 522 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 523 #define TEGRA186_CLK_I2C6 125 524 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 525 #define TEGRA186_CLK_UART_FST_MIPI_CAL 126 526 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 527 #define TEGRA186_CLK_VIC 127 528 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ 529 #define TEGRA186_CLK_SDMMC_LEGACY_TM 128 530 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 531 #define TEGRA186_CLK_NVDEC 129 532 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 533 #define TEGRA186_CLK_NVJPG 130 534 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 535 #define TEGRA186_CLK_NVENC 131 536 /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 537 #define TEGRA186_CLK_QSPI 132 538 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ 539 #define TEGRA186_CLK_VI_I2C 133 540 /** @brief output of gate CLK_ENB_HSIC_TRK */ 541 #define TEGRA186_CLK_HSIC_TRK 134 542 /** @brief output of gate CLK_ENB_USB2_TRK */ 543 #define TEGRA186_CLK_USB2_TRK 135 544 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ 545 #define TEGRA186_CLK_MAUD 136 546 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ 547 #define TEGRA186_CLK_TSECB 137 548 /** @brief output of gate CLK_ENB_ADSP */ 549 #define TEGRA186_CLK_ADSP 138 550 /** @brief output of gate CLK_ENB_ADSPNEON */ 551 #define TEGRA186_CLK_ADSPNEON 139 552 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 553 #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 554 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 555 #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 556 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 557 #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 558 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 559 #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 560 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 561 #define TEGRA186_CLK_MPHY_L0_RX_ANA 144 562 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 563 #define TEGRA186_CLK_MPHY_L1_RX_ANA 145 564 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ 565 #define TEGRA186_CLK_MPHY_IOBIST 146 566 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 567 #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 568 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 569 #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 570 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 571 #define TEGRA186_CLK_AXI_CBB 149 572 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 573 #define TEGRA186_CLK_DMIC3 150 574 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 575 #define TEGRA186_CLK_DMIC4 151 576 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 577 #define TEGRA186_CLK_DSPK1 152 578 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 579 #define TEGRA186_CLK_DSPK2 153 580 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 581 #define TEGRA186_CLK_I2S6 154 582 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ 583 #define TEGRA186_CLK_NVDISPLAY_P0 155 584 /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ 585 #define TEGRA186_CLK_NVDISPLAY_DISP 156 586 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ 587 #define TEGRA186_CLK_NVDISPLAY_DSC 157 588 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ 589 #define TEGRA186_CLK_NVDISPLAYHUB 158 590 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ 591 #define TEGRA186_CLK_NVDISPLAY_P1 159 592 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ 593 #define TEGRA186_CLK_NVDISPLAY_P2 160 594 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ 595 #define TEGRA186_CLK_TACH 166 596 /** @brief output of gate CLK_ENB_EQOS */ 597 #define TEGRA186_CLK_EQOS_AXI 167 598 /** @brief output of gate CLK_ENB_EQOS_RX */ 599 #define TEGRA186_CLK_EQOS_RX 168 600 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 601 #define TEGRA186_CLK_UFSHC 178 602 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 603 #define TEGRA186_CLK_UFSDEV_REF 179 604 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 605 #define TEGRA186_CLK_NVCSI 180 606 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 607 #define TEGRA186_CLK_NVCSILP 181 608 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 609 #define TEGRA186_CLK_I2C7 182 610 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 611 #define TEGRA186_CLK_I2C9 183 612 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ 613 #define TEGRA186_CLK_I2C12 184 614 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ 615 #define TEGRA186_CLK_I2C13 185 616 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ 617 #define TEGRA186_CLK_I2C14 186 618 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 619 #define TEGRA186_CLK_PWM1 187 620 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 621 #define TEGRA186_CLK_PWM2 188 622 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 623 #define TEGRA186_CLK_PWM3 189 624 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 625 #define TEGRA186_CLK_PWM5 190 626 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 627 #define TEGRA186_CLK_PWM6 191 628 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 629 #define TEGRA186_CLK_PWM7 192 630 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 631 #define TEGRA186_CLK_PWM8 193 632 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 633 #define TEGRA186_CLK_UARTE 194 634 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 635 #define TEGRA186_CLK_UARTF 195 636 /** @deprecated */ 637 #define TEGRA186_CLK_DBGAPB 196 638 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ 639 #define TEGRA186_CLK_BPMP_CPU_NIC 197 640 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ 641 #define TEGRA186_CLK_BPMP_APB 199 642 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ 643 #define TEGRA186_CLK_ACTMON 201 644 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ 645 #define TEGRA186_CLK_AON_CPU_NIC 208 646 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 647 #define TEGRA186_CLK_CAN1 210 648 /** @brief output of gate CLK_ENB_CAN1_HOST */ 649 #define TEGRA186_CLK_CAN1_HOST 211 650 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 651 #define TEGRA186_CLK_CAN2 212 652 /** @brief output of gate CLK_ENB_CAN2_HOST */ 653 #define TEGRA186_CLK_CAN2_HOST 213 654 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ 655 #define TEGRA186_CLK_AON_APB 214 656 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 657 #define TEGRA186_CLK_UARTC 215 658 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ 659 #define TEGRA186_CLK_UARTG 216 660 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 661 #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 662 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 663 #define TEGRA186_CLK_I2C2 218 664 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 665 #define TEGRA186_CLK_I2C8 219 666 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ 667 #define TEGRA186_CLK_I2C10 220 668 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ 669 #define TEGRA186_CLK_AON_I2C_SLOW 221 670 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 671 #define TEGRA186_CLK_SPI2 222 672 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 673 #define TEGRA186_CLK_DMIC5 223 674 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ 675 #define TEGRA186_CLK_AON_TOUCH 224 676 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 677 #define TEGRA186_CLK_PWM4 225 678 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ 679 #define TEGRA186_CLK_TSC 226 680 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ 681 #define TEGRA186_CLK_MSS_ENCRYPT 227 682 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 683 #define TEGRA186_CLK_SCE_CPU_NIC 228 684 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ 685 #define TEGRA186_CLK_SCE_APB 230 686 /** @brief output of gate CLK_ENB_DSIC */ 687 #define TEGRA186_CLK_DSIC 231 688 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ 689 #define TEGRA186_CLK_DSIC_LP 232 690 /** @brief output of gate CLK_ENB_DSID */ 691 #define TEGRA186_CLK_DSID 233 692 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ 693 #define TEGRA186_CLK_DSID_LP 234 694 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ 695 #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 696 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ 697 #define TEGRA186_CLK_SPDIF_OUT 238 698 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ 699 #define TEGRA186_CLK_EQOS_PTP_REF 239 700 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ 701 #define TEGRA186_CLK_EQOS_TX 240 702 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ 703 #define TEGRA186_CLK_USB2_HSIC_TRK 241 704 /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ 705 #define TEGRA186_CLK_XUSB_CORE_SS 242 706 /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ 707 #define TEGRA186_CLK_XUSB_CORE_DEV 243 708 /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ 709 #define TEGRA186_CLK_XUSB_FALCON 244 710 /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ 711 #define TEGRA186_CLK_XUSB_FS 245 712 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 713 #define TEGRA186_CLK_PLL_A_OUT0 246 714 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 715 #define TEGRA186_CLK_SYNC_I2S1 247 716 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 717 #define TEGRA186_CLK_SYNC_I2S2 248 718 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 719 #define TEGRA186_CLK_SYNC_I2S3 249 720 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 721 #define TEGRA186_CLK_SYNC_I2S4 250 722 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 723 #define TEGRA186_CLK_SYNC_I2S5 251 724 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 725 #define TEGRA186_CLK_SYNC_I2S6 252 726 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 727 #define TEGRA186_CLK_SYNC_DSPK1 253 728 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 729 #define TEGRA186_CLK_SYNC_DSPK2 254 730 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 731 #define TEGRA186_CLK_SYNC_DMIC1 255 732 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 733 #define TEGRA186_CLK_SYNC_DMIC2 256 734 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 735 #define TEGRA186_CLK_SYNC_DMIC3 257 736 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 737 #define TEGRA186_CLK_SYNC_DMIC4 259 738 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ 739 #define TEGRA186_CLK_SYNC_SPDIF 260 740 /** @brief output of gate CLK_ENB_PLLREFE_OUT */ 741 #define TEGRA186_CLK_PLLREFE_OUT_GATED 261 742 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: 743 * * VCO/pdiv defined by this clock object 744 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT 745 */ 746 #define TEGRA186_CLK_PLLREFE_OUT1 262 747 #define TEGRA186_CLK_PLLD_OUT1 267 748 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ 749 #define TEGRA186_CLK_PLLP_OUT0 269 750 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ 751 #define TEGRA186_CLK_PLLP_OUT5 270 752 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 753 #define TEGRA186_CLK_PLLA 271 754 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ 755 #define TEGRA186_CLK_ACLK 273 756 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ 757 #define TEGRA186_CLK_PLL_U_48M 274 758 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ 759 #define TEGRA186_CLK_PLL_U_480M 275 760 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ 761 #define TEGRA186_CLK_PLLC4_OUT0 276 762 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ 763 #define TEGRA186_CLK_PLLC4_OUT1 277 764 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ 765 #define TEGRA186_CLK_PLLC4_OUT2 278 766 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ 767 #define TEGRA186_CLK_PLLC4_OUT_MUX 279 768 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 769 #define TEGRA186_CLK_DFLLDISP_DIV 284 770 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ 771 #define TEGRA186_CLK_PLLDISPHUB_DIV 285 772 /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ 773 #define TEGRA186_CLK_PLLP_DIV8 286 774 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ 775 #define TEGRA186_CLK_BPMP_NIC 287 776 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ 777 #define TEGRA186_CLK_PLL_A_OUT1 288 778 /** @deprecated */ 779 #define TEGRA186_CLK_GPC2CLK 289 780 /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ 781 #define TEGRA186_CLK_KFUSE 293 782 /** 783 * @brief controls the PLLE hardware sequencer. 784 * @details This clock only has enable and disable methods. When the 785 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by 786 * hw based on the control signals from the PCIe, SATA and XUSB 787 * clocks. When the PLLE hw sequencer is disabled, the state of PLLE 788 * is controlled by sw using clk_enable/clk_disable on 789 * TEGRA186_CLK_PLLE. 790 */ 791 #define TEGRA186_CLK_PLLE_PWRSEQ 294 792 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ 793 #define TEGRA186_CLK_PLLREFE_REF 295 794 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ 795 #define TEGRA186_CLK_SOR0_OUT 296 796 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ 797 #define TEGRA186_CLK_SOR1_OUT 297 798 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ 799 #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 800 /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ 801 #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 802 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ 803 #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 804 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ 805 #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 806 /** @brief controls the UPHY_PLL0 hardware sqeuencer */ 807 #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 808 /** @brief controls the UPHY_PLL1 hardware sqeuencer */ 809 #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 810 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ 811 #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 812 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ 813 #define TEGRA186_CLK_PLLREFE_PEX 307 814 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ 815 #define TEGRA186_CLK_PLLREFE_IDDQ 308 816 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ 817 #define TEGRA186_CLK_QSPI_OUT 309 818 /** 819 * @brief GPC2CLK-div-2 820 * @details fixed /2 divider. Output frequency is 821 * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the 822 * frequency at which the GPU graphics engine runs. */ 823 #define TEGRA186_CLK_GPCCLK 310 824 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ 825 #define TEGRA186_CLK_AON_NIC 450 826 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 827 #define TEGRA186_CLK_SCE_NIC 451 828 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 829 #define TEGRA186_CLK_PLLE 512 830 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 831 #define TEGRA186_CLK_PLLC 513 832 /** Fixed 408MHz PLL for use by peripheral clocks */ 833 #define TEGRA186_CLK_PLLP 516 834 /** @deprecated */ 835 #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP 836 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ 837 #define TEGRA186_CLK_PLLD 518 838 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ 839 #define TEGRA186_CLK_PLLD2 519 840 /** 841 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. 842 * @details Note that this clock only controls the VCO output, before 843 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more 844 * information. 845 */ 846 #define TEGRA186_CLK_PLLREFE_VCO 520 847 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 848 #define TEGRA186_CLK_PLLC2 521 849 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ 850 #define TEGRA186_CLK_PLLC3 522 851 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ 852 #define TEGRA186_CLK_PLLDP 523 853 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 854 #define TEGRA186_CLK_PLLC4_VCO 524 855 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 856 #define TEGRA186_CLK_PLLA1 525 857 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 858 #define TEGRA186_CLK_PLLNVCSI 526 859 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ 860 #define TEGRA186_CLK_PLLDISPHUB 527 861 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ 862 #define TEGRA186_CLK_PLLD3 528 863 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ 864 #define TEGRA186_CLK_PLLBPMPCAM 531 865 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 866 #define TEGRA186_CLK_PLLAON 532 867 /** Fixed frequency 960MHz PLL for USB and EAVB */ 868 #define TEGRA186_CLK_PLLU 533 869 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ 870 #define TEGRA186_CLK_PLLC4_VCO_DIV2 535 871 /** @brief NAFLL clock source for AXI_CBB */ 872 #define TEGRA186_CLK_NAFLL_AXI_CBB 564 873 /** @brief NAFLL clock source for BPMP */ 874 #define TEGRA186_CLK_NAFLL_BPMP 565 875 /** @brief NAFLL clock source for ISP */ 876 #define TEGRA186_CLK_NAFLL_ISP 566 877 /** @brief NAFLL clock source for NVDEC */ 878 #define TEGRA186_CLK_NAFLL_NVDEC 567 879 /** @brief NAFLL clock source for NVENC */ 880 #define TEGRA186_CLK_NAFLL_NVENC 568 881 /** @brief NAFLL clock source for NVJPG */ 882 #define TEGRA186_CLK_NAFLL_NVJPG 569 883 /** @brief NAFLL clock source for SCE */ 884 #define TEGRA186_CLK_NAFLL_SCE 570 885 /** @brief NAFLL clock source for SE */ 886 #define TEGRA186_CLK_NAFLL_SE 571 887 /** @brief NAFLL clock source for TSEC */ 888 #define TEGRA186_CLK_NAFLL_TSEC 572 889 /** @brief NAFLL clock source for TSECB */ 890 #define TEGRA186_CLK_NAFLL_TSECB 573 891 /** @brief NAFLL clock source for VI */ 892 #define TEGRA186_CLK_NAFLL_VI 574 893 /** @brief NAFLL clock source for VIC */ 894 #define TEGRA186_CLK_NAFLL_VIC 575 895 /** @brief NAFLL clock source for DISP */ 896 #define TEGRA186_CLK_NAFLL_DISP 576 897 /** @brief NAFLL clock source for GPU */ 898 #define TEGRA186_CLK_NAFLL_GPU 577 899 /** @brief NAFLL clock source for M-CPU cluster */ 900 #define TEGRA186_CLK_NAFLL_MCPU 578 901 /** @brief NAFLL clock source for B-CPU cluster */ 902 #define TEGRA186_CLK_NAFLL_BCPU 579 903 /** @brief input from Tegra's CLK_32K_IN pad */ 904 #define TEGRA186_CLK_CLK_32K 608 905 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 906 #define TEGRA186_CLK_CLK_M 609 907 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ 908 #define TEGRA186_CLK_PLL_REF 610 909 /** @brief input from Tegra's XTAL_IN */ 910 #define TEGRA186_CLK_OSC 612 911 /** @brief clock recovered from EAVB input */ 912 #define TEGRA186_CLK_EQOS_RX_INPUT 613 913 /** @brief clock recovered from DTV input */ 914 #define TEGRA186_CLK_DTV_INPUT 614 915 /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ 916 #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 917 /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ 918 #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 919 /** @brief clock recovered from I2S1 input */ 920 #define TEGRA186_CLK_I2S1_SYNC_INPUT 617 921 /** @brief clock recovered from I2S2 input */ 922 #define TEGRA186_CLK_I2S2_SYNC_INPUT 618 923 /** @brief clock recovered from I2S3 input */ 924 #define TEGRA186_CLK_I2S3_SYNC_INPUT 619 925 /** @brief clock recovered from I2S4 input */ 926 #define TEGRA186_CLK_I2S4_SYNC_INPUT 620 927 /** @brief clock recovered from I2S5 input */ 928 #define TEGRA186_CLK_I2S5_SYNC_INPUT 621 929 /** @brief clock recovered from I2S6 input */ 930 #define TEGRA186_CLK_I2S6_SYNC_INPUT 622 931 /** @brief clock recovered from SPDIFIN input */ 932 #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 933 934 /** 935 * @brief subject to change 936 * @details maximum clock identifier value plus one. 937 */ 938 #define TEGRA186_CLK_CLK_MAX 624 939 940 /** @} */ 941 942 #endif 943
Indexes created Wed Oct 15 16:09:53 GMT 2025