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      1  1.1  jmcneill /*	$NetBSD: tegra234-clock.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4  1.1  jmcneill /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
      5  1.1  jmcneill 
      6  1.1  jmcneill #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
      7  1.1  jmcneill #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
      8  1.1  jmcneill 
      9  1.1  jmcneill /** @brief output of gate CLK_ENB_FUSE */
     10  1.1  jmcneill #define TEGRA234_CLK_FUSE			40
     11  1.1  jmcneill /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
     12  1.1  jmcneill #define TEGRA234_CLK_SDMMC4			123
     13  1.1  jmcneill /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
     14  1.1  jmcneill #define TEGRA234_CLK_UARTA			155
     15  1.1  jmcneill 
     16  1.1  jmcneill #endif
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