tegra30-car.h revision 1.1.1.3
1/* $NetBSD: tegra30-car.h,v 1.1.1.3 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * This header provides constants for binding nvidia,tegra30-car. 6 * 7 * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 8 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 9 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 10 * this case, those clocks are assigned IDs above 160 in order to highlight 11 * this issue. Implementations that interpret these clock IDs as bit values 12 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 13 * explicitly handle these special cases. 14 * 15 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 16 * above. 17 */ 18 19#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 20#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 21 22#define TEGRA30_CLK_CPU 0 23/* 1 */ 24/* 2 */ 25/* 3 */ 26#define TEGRA30_CLK_RTC 4 27#define TEGRA30_CLK_TIMER 5 28#define TEGRA30_CLK_UARTA 6 29/* 7 (register bit affects uartb and vfir) */ 30#define TEGRA30_CLK_GPIO 8 31#define TEGRA30_CLK_SDMMC2 9 32/* 10 (register bit affects spdif_in and spdif_out) */ 33#define TEGRA30_CLK_I2S1 11 34#define TEGRA30_CLK_I2C1 12 35#define TEGRA30_CLK_NDFLASH 13 36#define TEGRA30_CLK_SDMMC1 14 37#define TEGRA30_CLK_SDMMC4 15 38/* 16 */ 39#define TEGRA30_CLK_PWM 17 40#define TEGRA30_CLK_I2S2 18 41#define TEGRA30_CLK_EPP 19 42/* 20 (register bit affects vi and vi_sensor) */ 43#define TEGRA30_CLK_GR2D 21 44#define TEGRA30_CLK_USBD 22 45#define TEGRA30_CLK_ISP 23 46#define TEGRA30_CLK_GR3D 24 47/* 25 */ 48#define TEGRA30_CLK_DISP2 26 49#define TEGRA30_CLK_DISP1 27 50#define TEGRA30_CLK_HOST1X 28 51#define TEGRA30_CLK_VCP 29 52#define TEGRA30_CLK_I2S0 30 53#define TEGRA30_CLK_COP_CACHE 31 54 55#define TEGRA30_CLK_MC 32 56#define TEGRA30_CLK_AHBDMA 33 57#define TEGRA30_CLK_APBDMA 34 58/* 35 */ 59#define TEGRA30_CLK_KBC 36 60#define TEGRA30_CLK_STATMON 37 61#define TEGRA30_CLK_PMC 38 62/* 39 (register bit affects fuse and fuse_burn) */ 63#define TEGRA30_CLK_KFUSE 40 64#define TEGRA30_CLK_SBC1 41 65#define TEGRA30_CLK_NOR 42 66/* 43 */ 67#define TEGRA30_CLK_SBC2 44 68/* 45 */ 69#define TEGRA30_CLK_SBC3 46 70#define TEGRA30_CLK_I2C5 47 71#define TEGRA30_CLK_DSIA 48 72/* 49 (register bit affects cve and tvo) */ 73#define TEGRA30_CLK_MIPI 50 74#define TEGRA30_CLK_HDMI 51 75#define TEGRA30_CLK_CSI 52 76#define TEGRA30_CLK_TVDAC 53 77#define TEGRA30_CLK_I2C2 54 78#define TEGRA30_CLK_UARTC 55 79/* 56 */ 80#define TEGRA30_CLK_EMC 57 81#define TEGRA30_CLK_USB2 58 82#define TEGRA30_CLK_USB3 59 83#define TEGRA30_CLK_MPE 60 84#define TEGRA30_CLK_VDE 61 85#define TEGRA30_CLK_BSEA 62 86#define TEGRA30_CLK_BSEV 63 87 88#define TEGRA30_CLK_SPEEDO 64 89#define TEGRA30_CLK_UARTD 65 90#define TEGRA30_CLK_UARTE 66 91#define TEGRA30_CLK_I2C3 67 92#define TEGRA30_CLK_SBC4 68 93#define TEGRA30_CLK_SDMMC3 69 94#define TEGRA30_CLK_PCIE 70 95#define TEGRA30_CLK_OWR 71 96#define TEGRA30_CLK_AFI 72 97#define TEGRA30_CLK_CSITE 73 98/* 74 */ 99#define TEGRA30_CLK_AVPUCQ 75 100#define TEGRA30_CLK_LA 76 101/* 77 */ 102/* 78 */ 103#define TEGRA30_CLK_DTV 79 104#define TEGRA30_CLK_NDSPEED 80 105#define TEGRA30_CLK_I2CSLOW 81 106#define TEGRA30_CLK_DSIB 82 107/* 83 */ 108#define TEGRA30_CLK_IRAMA 84 109#define TEGRA30_CLK_IRAMB 85 110#define TEGRA30_CLK_IRAMC 86 111#define TEGRA30_CLK_IRAMD 87 112#define TEGRA30_CLK_CRAM2 88 113/* 89 */ 114#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 115/* 91 */ 116#define TEGRA30_CLK_CSUS 92 117#define TEGRA30_CLK_CDEV2 93 118#define TEGRA30_CLK_CDEV1 94 119/* 95 */ 120 121#define TEGRA30_CLK_CPU_G 96 122#define TEGRA30_CLK_CPU_LP 97 123#define TEGRA30_CLK_GR3D2 98 124#define TEGRA30_CLK_MSELECT 99 125#define TEGRA30_CLK_TSENSOR 100 126#define TEGRA30_CLK_I2S3 101 127#define TEGRA30_CLK_I2S4 102 128#define TEGRA30_CLK_I2C4 103 129#define TEGRA30_CLK_SBC5 104 130#define TEGRA30_CLK_SBC6 105 131#define TEGRA30_CLK_D_AUDIO 106 132#define TEGRA30_CLK_APBIF 107 133#define TEGRA30_CLK_DAM0 108 134#define TEGRA30_CLK_DAM1 109 135#define TEGRA30_CLK_DAM2 110 136#define TEGRA30_CLK_HDA2CODEC_2X 111 137#define TEGRA30_CLK_ATOMICS 112 138#define TEGRA30_CLK_AUDIO0_2X 113 139#define TEGRA30_CLK_AUDIO1_2X 114 140#define TEGRA30_CLK_AUDIO2_2X 115 141#define TEGRA30_CLK_AUDIO3_2X 116 142#define TEGRA30_CLK_AUDIO4_2X 117 143#define TEGRA30_CLK_SPDIF_2X 118 144#define TEGRA30_CLK_ACTMON 119 145#define TEGRA30_CLK_EXTERN1 120 146#define TEGRA30_CLK_EXTERN2 121 147#define TEGRA30_CLK_EXTERN3 122 148#define TEGRA30_CLK_SATA_OOB 123 149#define TEGRA30_CLK_SATA 124 150#define TEGRA30_CLK_HDA 125 151/* 126 */ 152#define TEGRA30_CLK_SE 127 153 154#define TEGRA30_CLK_HDA2HDMI 128 155#define TEGRA30_CLK_SATA_COLD 129 156/* 130 */ 157/* 131 */ 158/* 132 */ 159/* 133 */ 160/* 134 */ 161/* 135 */ 162#define TEGRA30_CLK_CEC 136 163/* 137 */ 164/* 138 */ 165/* 139 */ 166/* 140 */ 167/* 141 */ 168/* 142 */ 169/* 143 */ 170/* 144 */ 171/* 145 */ 172/* 146 */ 173/* 147 */ 174/* 148 */ 175/* 149 */ 176/* 150 */ 177/* 151 */ 178/* 152 */ 179/* 153 */ 180/* 154 */ 181/* 155 */ 182/* 156 */ 183/* 157 */ 184/* 158 */ 185/* 159 */ 186 187#define TEGRA30_CLK_UARTB 160 188#define TEGRA30_CLK_VFIR 161 189#define TEGRA30_CLK_SPDIF_IN 162 190#define TEGRA30_CLK_SPDIF_OUT 163 191#define TEGRA30_CLK_VI 164 192#define TEGRA30_CLK_VI_SENSOR 165 193#define TEGRA30_CLK_FUSE 166 194#define TEGRA30_CLK_FUSE_BURN 167 195#define TEGRA30_CLK_CVE 168 196#define TEGRA30_CLK_TVO 169 197#define TEGRA30_CLK_CLK_32K 170 198#define TEGRA30_CLK_CLK_M 171 199#define TEGRA30_CLK_CLK_M_DIV2 172 200#define TEGRA30_CLK_CLK_M_DIV4 173 201#define TEGRA30_CLK_PLL_REF 174 202#define TEGRA30_CLK_PLL_C 175 203#define TEGRA30_CLK_PLL_C_OUT1 176 204#define TEGRA30_CLK_PLL_M 177 205#define TEGRA30_CLK_PLL_M_OUT1 178 206#define TEGRA30_CLK_PLL_P 179 207#define TEGRA30_CLK_PLL_P_OUT1 180 208#define TEGRA30_CLK_PLL_P_OUT2 181 209#define TEGRA30_CLK_PLL_P_OUT3 182 210#define TEGRA30_CLK_PLL_P_OUT4 183 211#define TEGRA30_CLK_PLL_A 184 212#define TEGRA30_CLK_PLL_A_OUT0 185 213#define TEGRA30_CLK_PLL_D 186 214#define TEGRA30_CLK_PLL_D_OUT0 187 215#define TEGRA30_CLK_PLL_D2 188 216#define TEGRA30_CLK_PLL_D2_OUT0 189 217#define TEGRA30_CLK_PLL_U 190 218#define TEGRA30_CLK_PLL_X 191 219 220#define TEGRA30_CLK_PLL_X_OUT0 192 221#define TEGRA30_CLK_PLL_E 193 222#define TEGRA30_CLK_SPDIF_IN_SYNC 194 223#define TEGRA30_CLK_I2S0_SYNC 195 224#define TEGRA30_CLK_I2S1_SYNC 196 225#define TEGRA30_CLK_I2S2_SYNC 197 226#define TEGRA30_CLK_I2S3_SYNC 198 227#define TEGRA30_CLK_I2S4_SYNC 199 228#define TEGRA30_CLK_VIMCLK_SYNC 200 229#define TEGRA30_CLK_AUDIO0 201 230#define TEGRA30_CLK_AUDIO1 202 231#define TEGRA30_CLK_AUDIO2 203 232#define TEGRA30_CLK_AUDIO3 204 233#define TEGRA30_CLK_AUDIO4 205 234#define TEGRA30_CLK_SPDIF 206 235#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ 236#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ 237#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ 238#define TEGRA30_CLK_SCLK 210 239#define TEGRA30_CLK_BLINK 211 240#define TEGRA30_CLK_CCLK_G 212 241#define TEGRA30_CLK_CCLK_LP 213 242#define TEGRA30_CLK_TWD 214 243#define TEGRA30_CLK_CML0 215 244#define TEGRA30_CLK_CML1 216 245#define TEGRA30_CLK_HCLK 217 246#define TEGRA30_CLK_PCLK 218 247/* 219 */ 248/* 220 */ 249/* 221 */ 250/* 222 */ 251/* 223 */ 252 253/* 288 */ 254/* 289 */ 255/* 290 */ 256/* 291 */ 257/* 292 */ 258/* 293 */ 259/* 294 */ 260/* 295 */ 261/* 296 */ 262/* 297 */ 263/* 298 */ 264/* 299 */ 265#define TEGRA30_CLK_CLK_OUT_1_MUX 300 266#define TEGRA30_CLK_CLK_OUT_2_MUX 301 267#define TEGRA30_CLK_CLK_OUT_3_MUX 302 268#define TEGRA30_CLK_AUDIO0_MUX 303 269#define TEGRA30_CLK_AUDIO1_MUX 304 270#define TEGRA30_CLK_AUDIO2_MUX 305 271#define TEGRA30_CLK_AUDIO3_MUX 306 272#define TEGRA30_CLK_AUDIO4_MUX 307 273#define TEGRA30_CLK_SPDIF_MUX 308 274#define TEGRA30_CLK_CLK_MAX 309 275 276#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 277