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      1  1.1  jmcneill /*	$NetBSD: jz4775-dma.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0-only */
      4  1.1  jmcneill /*
      5  1.1  jmcneill  * This header provides macros for JZ4775 DMA bindings.
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Copyright (c) 2020  (Zhou Yanjie) <zhouyanjie (at) wanyeetech.com>
      8  1.1  jmcneill  */
      9  1.1  jmcneill 
     10  1.1  jmcneill #ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
     11  1.1  jmcneill #define __DT_BINDINGS_DMA_JZ4775_DMA_H__
     12  1.1  jmcneill 
     13  1.1  jmcneill /*
     14  1.1  jmcneill  * Request type numbers for the JZ4775 DMA controller (written to the DRTn
     15  1.1  jmcneill  * register for the channel).
     16  1.1  jmcneill  */
     17  1.1  jmcneill #define JZ4775_DMA_I2S0_TX	0x6
     18  1.1  jmcneill #define JZ4775_DMA_I2S0_RX	0x7
     19  1.1  jmcneill #define JZ4775_DMA_AUTO		0x8
     20  1.1  jmcneill #define JZ4775_DMA_SADC_RX	0x9
     21  1.1  jmcneill #define JZ4775_DMA_UART3_TX	0x0e
     22  1.1  jmcneill #define JZ4775_DMA_UART3_RX	0x0f
     23  1.1  jmcneill #define JZ4775_DMA_UART2_TX	0x10
     24  1.1  jmcneill #define JZ4775_DMA_UART2_RX	0x11
     25  1.1  jmcneill #define JZ4775_DMA_UART1_TX	0x12
     26  1.1  jmcneill #define JZ4775_DMA_UART1_RX	0x13
     27  1.1  jmcneill #define JZ4775_DMA_UART0_TX	0x14
     28  1.1  jmcneill #define JZ4775_DMA_UART0_RX	0x15
     29  1.1  jmcneill #define JZ4775_DMA_SSI0_TX	0x16
     30  1.1  jmcneill #define JZ4775_DMA_SSI0_RX	0x17
     31  1.1  jmcneill #define JZ4775_DMA_MSC0_TX	0x1a
     32  1.1  jmcneill #define JZ4775_DMA_MSC0_RX	0x1b
     33  1.1  jmcneill #define JZ4775_DMA_MSC1_TX	0x1c
     34  1.1  jmcneill #define JZ4775_DMA_MSC1_RX	0x1d
     35  1.1  jmcneill #define JZ4775_DMA_MSC2_TX	0x1e
     36  1.1  jmcneill #define JZ4775_DMA_MSC2_RX	0x1f
     37  1.1  jmcneill #define JZ4775_DMA_PCM0_TX	0x20
     38  1.1  jmcneill #define JZ4775_DMA_PCM0_RX	0x21
     39  1.1  jmcneill #define JZ4775_DMA_SMB0_TX	0x24
     40  1.1  jmcneill #define JZ4775_DMA_SMB0_RX	0x25
     41  1.1  jmcneill #define JZ4775_DMA_SMB1_TX	0x26
     42  1.1  jmcneill #define JZ4775_DMA_SMB1_RX	0x27
     43  1.1  jmcneill #define JZ4775_DMA_SMB2_TX	0x28
     44  1.1  jmcneill #define JZ4775_DMA_SMB2_RX	0x29
     45  1.1  jmcneill 
     46  1.1  jmcneill #endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */
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