1 1.1 jmcneill /* $NetBSD: tegra194-gpio.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 5 1.1 jmcneill 6 1.1 jmcneill /* 7 1.1 jmcneill * This header provides constants for binding nvidia,tegra194-gpio*. 8 1.1 jmcneill * 9 1.1 jmcneill * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 10 1.1 jmcneill * provide names for this. 11 1.1 jmcneill * 12 1.1 jmcneill * The second cell contains standard flag values specified in gpio.h. 13 1.1 jmcneill */ 14 1.1 jmcneill 15 1.1 jmcneill #ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 16 1.1 jmcneill #define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 17 1.1 jmcneill 18 1.1 jmcneill #include <dt-bindings/gpio/gpio.h> 19 1.1 jmcneill 20 1.1 jmcneill /* GPIOs implemented by main GPIO controller */ 21 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_A 0 22 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_B 1 23 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_C 2 24 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_D 3 25 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_E 4 26 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_F 5 27 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_G 6 28 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_H 7 29 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_I 8 30 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_J 9 31 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_K 10 32 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_L 11 33 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_M 12 34 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_N 13 35 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_O 14 36 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_P 15 37 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_Q 16 38 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_R 17 39 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_S 18 40 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_T 19 41 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_U 20 42 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_V 21 43 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_W 22 44 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_X 23 45 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_Y 24 46 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_Z 25 47 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_FF 26 48 1.1 jmcneill #define TEGRA194_MAIN_GPIO_PORT_GG 27 49 1.1 jmcneill 50 1.1 jmcneill #define TEGRA194_MAIN_GPIO(port, offset) \ 51 1.1 jmcneill ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) 52 1.1 jmcneill 53 1.1 jmcneill /* GPIOs implemented by AON GPIO controller */ 54 1.1 jmcneill #define TEGRA194_AON_GPIO_PORT_AA 0 55 1.1 jmcneill #define TEGRA194_AON_GPIO_PORT_BB 1 56 1.1 jmcneill #define TEGRA194_AON_GPIO_PORT_CC 2 57 1.1 jmcneill #define TEGRA194_AON_GPIO_PORT_DD 3 58 1.1 jmcneill #define TEGRA194_AON_GPIO_PORT_EE 4 59 1.1 jmcneill 60 1.1 jmcneill #define TEGRA194_AON_GPIO(port, offset) \ 61 1.1 jmcneill ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) 62 1.1 jmcneill 63 1.1 jmcneill #endif 64