11.1Sskrll/* $NetBSD: tegra234-gpio.h,v 1.1.1.1 2026/01/18 05:21:44 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sskrll/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ 51.1Sskrll 61.1Sskrll/* 71.1Sskrll * This header provides constants for binding nvidia,tegra234-gpio*. 81.1Sskrll * 91.1Sskrll * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 101.1Sskrll * provide names for this. 111.1Sskrll * 121.1Sskrll * The second cell contains standard flag values specified in gpio.h. 131.1Sskrll */ 141.1Sskrll 151.1Sskrll#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 161.1Sskrll#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 171.1Sskrll 181.1Sskrll#include <dt-bindings/gpio/gpio.h> 191.1Sskrll 201.1Sskrll/* GPIOs implemented by main GPIO controller */ 211.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_A 0 221.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_B 1 231.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_C 2 241.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_D 3 251.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_E 4 261.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_F 5 271.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_G 6 281.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_H 7 291.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_I 8 301.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_J 9 311.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_K 10 321.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_L 11 331.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_M 12 341.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_N 13 351.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_P 14 361.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_Q 15 371.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_R 16 381.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_X 17 391.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_Y 18 401.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_Z 19 411.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_AC 20 421.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_AD 21 431.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_AE 22 441.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_AF 23 451.1Sskrll#define TEGRA234_MAIN_GPIO_PORT_AG 24 461.1Sskrll 471.1Sskrll#define TEGRA234_MAIN_GPIO(port, offset) \ 481.1Sskrll ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) 491.1Sskrll 501.1Sskrll/* GPIOs implemented by AON GPIO controller */ 511.1Sskrll#define TEGRA234_AON_GPIO_PORT_AA 0 521.1Sskrll#define TEGRA234_AON_GPIO_PORT_BB 1 531.1Sskrll#define TEGRA234_AON_GPIO_PORT_CC 2 541.1Sskrll#define TEGRA234_AON_GPIO_PORT_DD 3 551.1Sskrll#define TEGRA234_AON_GPIO_PORT_EE 4 561.1Sskrll#define TEGRA234_AON_GPIO_PORT_GG 5 571.1Sskrll 581.1Sskrll#define TEGRA234_AON_GPIO(port, offset) \ 591.1Sskrll ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) 601.1Sskrll 611.1Sskrll#endif 62