11.1Sjmcneill/* $NetBSD: qcom,spmi-vadc.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $ */ 21.1Sjmcneill 31.1.1.2Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/* 51.1.1.3Sjmcneill * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. 61.1Sjmcneill */ 71.1Sjmcneill 81.1Sjmcneill#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 91.1Sjmcneill#define _DT_BINDINGS_QCOM_SPMI_VADC_H 101.1Sjmcneill 111.1Sjmcneill/* Voltage ADC channels */ 121.1Sjmcneill#define VADC_USBIN 0x00 131.1Sjmcneill#define VADC_DCIN 0x01 141.1Sjmcneill#define VADC_VCHG_SNS 0x02 151.1Sjmcneill#define VADC_SPARE1_03 0x03 161.1Sjmcneill#define VADC_USB_ID_MV 0x04 171.1Sjmcneill#define VADC_VCOIN 0x05 181.1Sjmcneill#define VADC_VBAT_SNS 0x06 191.1Sjmcneill#define VADC_VSYS 0x07 201.1Sjmcneill#define VADC_DIE_TEMP 0x08 211.1Sjmcneill#define VADC_REF_625MV 0x09 221.1Sjmcneill#define VADC_REF_1250MV 0x0a 231.1Sjmcneill#define VADC_CHG_TEMP 0x0b 241.1Sjmcneill#define VADC_SPARE1 0x0c 251.1Sjmcneill#define VADC_SPARE2 0x0d 261.1Sjmcneill#define VADC_GND_REF 0x0e 271.1Sjmcneill#define VADC_VDD_VADC 0x0f 281.1Sjmcneill 291.1Sjmcneill#define VADC_P_MUX1_1_1 0x10 301.1Sjmcneill#define VADC_P_MUX2_1_1 0x11 311.1Sjmcneill#define VADC_P_MUX3_1_1 0x12 321.1Sjmcneill#define VADC_P_MUX4_1_1 0x13 331.1Sjmcneill#define VADC_P_MUX5_1_1 0x14 341.1Sjmcneill#define VADC_P_MUX6_1_1 0x15 351.1Sjmcneill#define VADC_P_MUX7_1_1 0x16 361.1Sjmcneill#define VADC_P_MUX8_1_1 0x17 371.1Sjmcneill#define VADC_P_MUX9_1_1 0x18 381.1Sjmcneill#define VADC_P_MUX10_1_1 0x19 391.1Sjmcneill#define VADC_P_MUX11_1_1 0x1a 401.1Sjmcneill#define VADC_P_MUX12_1_1 0x1b 411.1Sjmcneill#define VADC_P_MUX13_1_1 0x1c 421.1Sjmcneill#define VADC_P_MUX14_1_1 0x1d 431.1Sjmcneill#define VADC_P_MUX15_1_1 0x1e 441.1Sjmcneill#define VADC_P_MUX16_1_1 0x1f 451.1Sjmcneill 461.1Sjmcneill#define VADC_P_MUX1_1_3 0x20 471.1Sjmcneill#define VADC_P_MUX2_1_3 0x21 481.1Sjmcneill#define VADC_P_MUX3_1_3 0x22 491.1Sjmcneill#define VADC_P_MUX4_1_3 0x23 501.1Sjmcneill#define VADC_P_MUX5_1_3 0x24 511.1Sjmcneill#define VADC_P_MUX6_1_3 0x25 521.1Sjmcneill#define VADC_P_MUX7_1_3 0x26 531.1Sjmcneill#define VADC_P_MUX8_1_3 0x27 541.1Sjmcneill#define VADC_P_MUX9_1_3 0x28 551.1Sjmcneill#define VADC_P_MUX10_1_3 0x29 561.1Sjmcneill#define VADC_P_MUX11_1_3 0x2a 571.1Sjmcneill#define VADC_P_MUX12_1_3 0x2b 581.1Sjmcneill#define VADC_P_MUX13_1_3 0x2c 591.1Sjmcneill#define VADC_P_MUX14_1_3 0x2d 601.1Sjmcneill#define VADC_P_MUX15_1_3 0x2e 611.1Sjmcneill#define VADC_P_MUX16_1_3 0x2f 621.1Sjmcneill 631.1Sjmcneill#define VADC_LR_MUX1_BAT_THERM 0x30 641.1Sjmcneill#define VADC_LR_MUX2_BAT_ID 0x31 651.1Sjmcneill#define VADC_LR_MUX3_XO_THERM 0x32 661.1Sjmcneill#define VADC_LR_MUX4_AMUX_THM1 0x33 671.1Sjmcneill#define VADC_LR_MUX5_AMUX_THM2 0x34 681.1Sjmcneill#define VADC_LR_MUX6_AMUX_THM3 0x35 691.1Sjmcneill#define VADC_LR_MUX7_HW_ID 0x36 701.1Sjmcneill#define VADC_LR_MUX8_AMUX_THM4 0x37 711.1Sjmcneill#define VADC_LR_MUX9_AMUX_THM5 0x38 721.1Sjmcneill#define VADC_LR_MUX10_USB_ID 0x39 731.1Sjmcneill#define VADC_AMUX_PU1 0x3a 741.1Sjmcneill#define VADC_AMUX_PU2 0x3b 751.1Sjmcneill#define VADC_LR_MUX3_BUF_XO_THERM 0x3c 761.1Sjmcneill 771.1Sjmcneill#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 781.1Sjmcneill#define VADC_LR_MUX2_PU1_BAT_ID 0x71 791.1Sjmcneill#define VADC_LR_MUX3_PU1_XO_THERM 0x72 801.1Sjmcneill#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 811.1Sjmcneill#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 821.1Sjmcneill#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 831.1Sjmcneill#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 841.1Sjmcneill#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 851.1Sjmcneill#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 861.1Sjmcneill#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 871.1Sjmcneill#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 881.1Sjmcneill 891.1Sjmcneill#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 901.1Sjmcneill#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 911.1Sjmcneill#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 921.1Sjmcneill#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 931.1Sjmcneill#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 941.1Sjmcneill#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 951.1Sjmcneill#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 961.1Sjmcneill#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 971.1Sjmcneill#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 981.1Sjmcneill#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 991.1Sjmcneill#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 1001.1Sjmcneill 1011.1Sjmcneill#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 1021.1Sjmcneill#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 1031.1Sjmcneill#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 1041.1Sjmcneill#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 1051.1Sjmcneill#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 1061.1Sjmcneill#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 1071.1Sjmcneill#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 1081.1Sjmcneill#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 1091.1Sjmcneill#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 1101.1Sjmcneill#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 1111.1Sjmcneill#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 1121.1Sjmcneill 1131.1.1.2Sjmcneill/* ADC channels for SPMI PMIC5 */ 1141.1.1.2Sjmcneill 1151.1.1.2Sjmcneill#define ADC5_REF_GND 0x00 1161.1.1.2Sjmcneill#define ADC5_1P25VREF 0x01 1171.1.1.2Sjmcneill#define ADC5_VREF_VADC 0x02 1181.1.1.2Sjmcneill#define ADC5_VREF_VADC5_DIV_3 0x82 1191.1.1.2Sjmcneill#define ADC5_VPH_PWR 0x83 1201.1.1.2Sjmcneill#define ADC5_VBAT_SNS 0x84 1211.1.1.2Sjmcneill#define ADC5_VCOIN 0x85 1221.1.1.2Sjmcneill#define ADC5_DIE_TEMP 0x06 1231.1.1.2Sjmcneill#define ADC5_USB_IN_I 0x07 1241.1.1.2Sjmcneill#define ADC5_USB_IN_V_16 0x08 1251.1.1.2Sjmcneill#define ADC5_CHG_TEMP 0x09 1261.1.1.2Sjmcneill#define ADC5_BAT_THERM 0x0a 1271.1.1.2Sjmcneill#define ADC5_BAT_ID 0x0b 1281.1.1.2Sjmcneill#define ADC5_XO_THERM 0x0c 1291.1.1.2Sjmcneill#define ADC5_AMUX_THM1 0x0d 1301.1.1.2Sjmcneill#define ADC5_AMUX_THM2 0x0e 1311.1.1.2Sjmcneill#define ADC5_AMUX_THM3 0x0f 1321.1.1.2Sjmcneill#define ADC5_AMUX_THM4 0x10 1331.1.1.2Sjmcneill#define ADC5_AMUX_THM5 0x11 1341.1.1.2Sjmcneill#define ADC5_GPIO1 0x12 1351.1.1.2Sjmcneill#define ADC5_GPIO2 0x13 1361.1.1.2Sjmcneill#define ADC5_GPIO3 0x14 1371.1.1.2Sjmcneill#define ADC5_GPIO4 0x15 1381.1.1.2Sjmcneill#define ADC5_GPIO5 0x16 1391.1.1.2Sjmcneill#define ADC5_GPIO6 0x17 1401.1.1.2Sjmcneill#define ADC5_GPIO7 0x18 1411.1.1.2Sjmcneill#define ADC5_SBUx 0x99 1421.1.1.2Sjmcneill#define ADC5_MID_CHG_DIV6 0x1e 1431.1.1.2Sjmcneill#define ADC5_OFF 0xff 1441.1.1.2Sjmcneill 1451.1.1.2Sjmcneill/* 30k pull-up1 */ 1461.1.1.2Sjmcneill#define ADC5_BAT_THERM_30K_PU 0x2a 1471.1.1.2Sjmcneill#define ADC5_BAT_ID_30K_PU 0x2b 1481.1.1.2Sjmcneill#define ADC5_XO_THERM_30K_PU 0x2c 1491.1.1.2Sjmcneill#define ADC5_AMUX_THM1_30K_PU 0x2d 1501.1.1.2Sjmcneill#define ADC5_AMUX_THM2_30K_PU 0x2e 1511.1.1.2Sjmcneill#define ADC5_AMUX_THM3_30K_PU 0x2f 1521.1.1.2Sjmcneill#define ADC5_AMUX_THM4_30K_PU 0x30 1531.1.1.2Sjmcneill#define ADC5_AMUX_THM5_30K_PU 0x31 1541.1.1.2Sjmcneill#define ADC5_GPIO1_30K_PU 0x32 1551.1.1.2Sjmcneill#define ADC5_GPIO2_30K_PU 0x33 1561.1.1.2Sjmcneill#define ADC5_GPIO3_30K_PU 0x34 1571.1.1.2Sjmcneill#define ADC5_GPIO4_30K_PU 0x35 1581.1.1.2Sjmcneill#define ADC5_GPIO5_30K_PU 0x36 1591.1.1.2Sjmcneill#define ADC5_GPIO6_30K_PU 0x37 1601.1.1.2Sjmcneill#define ADC5_GPIO7_30K_PU 0x38 1611.1.1.2Sjmcneill#define ADC5_SBUx_30K_PU 0x39 1621.1.1.2Sjmcneill 1631.1.1.2Sjmcneill/* 100k pull-up2 */ 1641.1.1.2Sjmcneill#define ADC5_BAT_THERM_100K_PU 0x4a 1651.1.1.2Sjmcneill#define ADC5_BAT_ID_100K_PU 0x4b 1661.1.1.2Sjmcneill#define ADC5_XO_THERM_100K_PU 0x4c 1671.1.1.2Sjmcneill#define ADC5_AMUX_THM1_100K_PU 0x4d 1681.1.1.2Sjmcneill#define ADC5_AMUX_THM2_100K_PU 0x4e 1691.1.1.2Sjmcneill#define ADC5_AMUX_THM3_100K_PU 0x4f 1701.1.1.2Sjmcneill#define ADC5_AMUX_THM4_100K_PU 0x50 1711.1.1.2Sjmcneill#define ADC5_AMUX_THM5_100K_PU 0x51 1721.1.1.2Sjmcneill#define ADC5_GPIO1_100K_PU 0x52 1731.1.1.2Sjmcneill#define ADC5_GPIO2_100K_PU 0x53 1741.1.1.2Sjmcneill#define ADC5_GPIO3_100K_PU 0x54 1751.1.1.2Sjmcneill#define ADC5_GPIO4_100K_PU 0x55 1761.1.1.2Sjmcneill#define ADC5_GPIO5_100K_PU 0x56 1771.1.1.2Sjmcneill#define ADC5_GPIO6_100K_PU 0x57 1781.1.1.2Sjmcneill#define ADC5_GPIO7_100K_PU 0x58 1791.1.1.2Sjmcneill#define ADC5_SBUx_100K_PU 0x59 1801.1.1.2Sjmcneill 1811.1.1.2Sjmcneill/* 400k pull-up3 */ 1821.1.1.2Sjmcneill#define ADC5_BAT_THERM_400K_PU 0x6a 1831.1.1.2Sjmcneill#define ADC5_BAT_ID_400K_PU 0x6b 1841.1.1.2Sjmcneill#define ADC5_XO_THERM_400K_PU 0x6c 1851.1.1.2Sjmcneill#define ADC5_AMUX_THM1_400K_PU 0x6d 1861.1.1.2Sjmcneill#define ADC5_AMUX_THM2_400K_PU 0x6e 1871.1.1.2Sjmcneill#define ADC5_AMUX_THM3_400K_PU 0x6f 1881.1.1.2Sjmcneill#define ADC5_AMUX_THM4_400K_PU 0x70 1891.1.1.2Sjmcneill#define ADC5_AMUX_THM5_400K_PU 0x71 1901.1.1.2Sjmcneill#define ADC5_GPIO1_400K_PU 0x72 1911.1.1.2Sjmcneill#define ADC5_GPIO2_400K_PU 0x73 1921.1.1.2Sjmcneill#define ADC5_GPIO3_400K_PU 0x74 1931.1.1.2Sjmcneill#define ADC5_GPIO4_400K_PU 0x75 1941.1.1.2Sjmcneill#define ADC5_GPIO5_400K_PU 0x76 1951.1.1.2Sjmcneill#define ADC5_GPIO6_400K_PU 0x77 1961.1.1.2Sjmcneill#define ADC5_GPIO7_400K_PU 0x78 1971.1.1.2Sjmcneill#define ADC5_SBUx_400K_PU 0x79 1981.1.1.2Sjmcneill 1991.1.1.2Sjmcneill/* 1/3 Divider */ 2001.1.1.2Sjmcneill#define ADC5_GPIO1_DIV3 0x92 2011.1.1.2Sjmcneill#define ADC5_GPIO2_DIV3 0x93 2021.1.1.2Sjmcneill#define ADC5_GPIO3_DIV3 0x94 2031.1.1.2Sjmcneill#define ADC5_GPIO4_DIV3 0x95 2041.1.1.2Sjmcneill#define ADC5_GPIO5_DIV3 0x96 2051.1.1.2Sjmcneill#define ADC5_GPIO6_DIV3 0x97 2061.1.1.2Sjmcneill#define ADC5_GPIO7_DIV3 0x98 2071.1.1.2Sjmcneill#define ADC5_SBUx_DIV3 0x99 2081.1.1.2Sjmcneill 2091.1.1.2Sjmcneill/* Current and combined current/voltage channels */ 2101.1.1.2Sjmcneill#define ADC5_INT_EXT_ISENSE 0xa1 2111.1.1.2Sjmcneill#define ADC5_PARALLEL_ISENSE 0xa5 2121.1.1.2Sjmcneill#define ADC5_CUR_REPLICA_VDS 0xa7 2131.1.1.2Sjmcneill#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 2141.1.1.2Sjmcneill#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 2151.1.1.2Sjmcneill#define ADC5_EXT_SENS_OFFSET 0xad 2161.1.1.2Sjmcneill 2171.1.1.2Sjmcneill#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 2181.1.1.2Sjmcneill#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 2191.1.1.2Sjmcneill#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 2201.1.1.2Sjmcneill#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 2211.1.1.2Sjmcneill#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 2221.1.1.2Sjmcneill#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 2231.1.1.2Sjmcneill 2241.1.1.2Sjmcneill#define ADC5_MAX_CHANNEL 0xc0 2251.1.1.2Sjmcneill 2261.1.1.3Sjmcneill/* ADC channels for ADC for PMIC7 */ 2271.1.1.3Sjmcneill 2281.1.1.3Sjmcneill#define ADC7_REF_GND 0x00 2291.1.1.3Sjmcneill#define ADC7_1P25VREF 0x01 2301.1.1.3Sjmcneill#define ADC7_VREF_VADC 0x02 2311.1.1.3Sjmcneill#define ADC7_DIE_TEMP 0x03 2321.1.1.3Sjmcneill 2331.1.1.3Sjmcneill#define ADC7_AMUX_THM1 0x04 2341.1.1.3Sjmcneill#define ADC7_AMUX_THM2 0x05 2351.1.1.3Sjmcneill#define ADC7_AMUX_THM3 0x06 2361.1.1.3Sjmcneill#define ADC7_AMUX_THM4 0x07 2371.1.1.3Sjmcneill#define ADC7_AMUX_THM5 0x08 2381.1.1.3Sjmcneill#define ADC7_AMUX_THM6 0x09 2391.1.1.3Sjmcneill#define ADC7_GPIO1 0x0a 2401.1.1.3Sjmcneill#define ADC7_GPIO2 0x0b 2411.1.1.3Sjmcneill#define ADC7_GPIO3 0x0c 2421.1.1.3Sjmcneill#define ADC7_GPIO4 0x0d 2431.1.1.3Sjmcneill 2441.1.1.3Sjmcneill#define ADC7_CHG_TEMP 0x10 2451.1.1.3Sjmcneill#define ADC7_USB_IN_V_16 0x11 2461.1.1.3Sjmcneill#define ADC7_VDC_16 0x12 2471.1.1.3Sjmcneill#define ADC7_CC1_ID 0x13 2481.1.1.3Sjmcneill#define ADC7_VREF_BAT_THERM 0x15 2491.1.1.3Sjmcneill#define ADC7_IIN_FB 0x17 2501.1.1.3Sjmcneill 2511.1.1.3Sjmcneill/* 30k pull-up1 */ 2521.1.1.3Sjmcneill#define ADC7_AMUX_THM1_30K_PU 0x24 2531.1.1.3Sjmcneill#define ADC7_AMUX_THM2_30K_PU 0x25 2541.1.1.3Sjmcneill#define ADC7_AMUX_THM3_30K_PU 0x26 2551.1.1.3Sjmcneill#define ADC7_AMUX_THM4_30K_PU 0x27 2561.1.1.3Sjmcneill#define ADC7_AMUX_THM5_30K_PU 0x28 2571.1.1.3Sjmcneill#define ADC7_AMUX_THM6_30K_PU 0x29 2581.1.1.3Sjmcneill#define ADC7_GPIO1_30K_PU 0x2a 2591.1.1.3Sjmcneill#define ADC7_GPIO2_30K_PU 0x2b 2601.1.1.3Sjmcneill#define ADC7_GPIO3_30K_PU 0x2c 2611.1.1.3Sjmcneill#define ADC7_GPIO4_30K_PU 0x2d 2621.1.1.3Sjmcneill#define ADC7_CC1_ID_30K_PU 0x33 2631.1.1.3Sjmcneill 2641.1.1.3Sjmcneill/* 100k pull-up2 */ 2651.1.1.3Sjmcneill#define ADC7_AMUX_THM1_100K_PU 0x44 2661.1.1.3Sjmcneill#define ADC7_AMUX_THM2_100K_PU 0x45 2671.1.1.3Sjmcneill#define ADC7_AMUX_THM3_100K_PU 0x46 2681.1.1.3Sjmcneill#define ADC7_AMUX_THM4_100K_PU 0x47 2691.1.1.3Sjmcneill#define ADC7_AMUX_THM5_100K_PU 0x48 2701.1.1.3Sjmcneill#define ADC7_AMUX_THM6_100K_PU 0x49 2711.1.1.3Sjmcneill#define ADC7_GPIO1_100K_PU 0x4a 2721.1.1.3Sjmcneill#define ADC7_GPIO2_100K_PU 0x4b 2731.1.1.3Sjmcneill#define ADC7_GPIO3_100K_PU 0x4c 2741.1.1.3Sjmcneill#define ADC7_GPIO4_100K_PU 0x4d 2751.1.1.3Sjmcneill#define ADC7_CC1_ID_100K_PU 0x53 2761.1.1.3Sjmcneill 2771.1.1.3Sjmcneill/* 400k pull-up3 */ 2781.1.1.3Sjmcneill#define ADC7_AMUX_THM1_400K_PU 0x64 2791.1.1.3Sjmcneill#define ADC7_AMUX_THM2_400K_PU 0x65 2801.1.1.3Sjmcneill#define ADC7_AMUX_THM3_400K_PU 0x66 2811.1.1.3Sjmcneill#define ADC7_AMUX_THM4_400K_PU 0x67 2821.1.1.3Sjmcneill#define ADC7_AMUX_THM5_400K_PU 0x68 2831.1.1.3Sjmcneill#define ADC7_AMUX_THM6_400K_PU 0x69 2841.1.1.3Sjmcneill#define ADC7_GPIO1_400K_PU 0x6a 2851.1.1.3Sjmcneill#define ADC7_GPIO2_400K_PU 0x6b 2861.1.1.3Sjmcneill#define ADC7_GPIO3_400K_PU 0x6c 2871.1.1.3Sjmcneill#define ADC7_GPIO4_400K_PU 0x6d 2881.1.1.3Sjmcneill#define ADC7_CC1_ID_400K_PU 0x73 2891.1.1.3Sjmcneill 2901.1.1.3Sjmcneill/* 1/3 Divider */ 2911.1.1.3Sjmcneill#define ADC7_GPIO1_DIV3 0x8a 2921.1.1.3Sjmcneill#define ADC7_GPIO2_DIV3 0x8b 2931.1.1.3Sjmcneill#define ADC7_GPIO3_DIV3 0x8c 2941.1.1.3Sjmcneill#define ADC7_GPIO4_DIV3 0x8d 2951.1.1.3Sjmcneill 2961.1.1.3Sjmcneill#define ADC7_VPH_PWR 0x8e 2971.1.1.3Sjmcneill#define ADC7_VBAT_SNS 0x8f 2981.1.1.3Sjmcneill 2991.1.1.3Sjmcneill#define ADC7_SBUx 0x94 3001.1.1.3Sjmcneill#define ADC7_VBAT_2S_MID 0x96 3011.1.1.3Sjmcneill 3021.1Sjmcneill#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 303