11.1Sskrll/* $NetBSD: fsl,imx8mp.h,v 1.1.1.1 2026/01/18 05:21:45 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 OR MIT */ 41.1Sskrll/* 51.1Sskrll * Interconnect framework driver for i.MX SoC 61.1Sskrll * 71.1Sskrll * Copyright 2022 NXP 81.1Sskrll * Peng Fan <peng.fan@nxp.com> 91.1Sskrll */ 101.1Sskrll 111.1Sskrll#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H 121.1Sskrll#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H 131.1Sskrll 141.1Sskrll#define IMX8MP_ICN_NOC 0 151.1Sskrll#define IMX8MP_ICN_MAIN 1 161.1Sskrll#define IMX8MP_ICS_DRAM 2 171.1Sskrll#define IMX8MP_ICS_OCRAM 3 181.1Sskrll#define IMX8MP_ICM_A53 4 191.1Sskrll#define IMX8MP_ICM_SUPERMIX 5 201.1Sskrll#define IMX8MP_ICM_GIC 6 211.1Sskrll#define IMX8MP_ICM_MLMIX 7 221.1Sskrll 231.1Sskrll#define IMX8MP_ICN_AUDIO 8 241.1Sskrll#define IMX8MP_ICM_DSP 9 251.1Sskrll#define IMX8MP_ICM_SDMA2PER 10 261.1Sskrll#define IMX8MP_ICM_SDMA2BURST 11 271.1Sskrll#define IMX8MP_ICM_SDMA3PER 12 281.1Sskrll#define IMX8MP_ICM_SDMA3BURST 13 291.1Sskrll#define IMX8MP_ICM_EDMA 14 301.1Sskrll 311.1Sskrll#define IMX8MP_ICN_GPU 15 321.1Sskrll#define IMX8MP_ICM_GPU2D 16 331.1Sskrll#define IMX8MP_ICM_GPU3D 17 341.1Sskrll 351.1Sskrll#define IMX8MP_ICN_HDMI 18 361.1Sskrll#define IMX8MP_ICM_HRV 19 371.1Sskrll#define IMX8MP_ICM_LCDIF_HDMI 20 381.1Sskrll#define IMX8MP_ICM_HDCP 21 391.1Sskrll 401.1Sskrll#define IMX8MP_ICN_HSIO 22 411.1Sskrll#define IMX8MP_ICM_NOC_PCIE 23 421.1Sskrll#define IMX8MP_ICM_USB1 24 431.1Sskrll#define IMX8MP_ICM_USB2 25 441.1Sskrll#define IMX8MP_ICM_PCIE 26 451.1Sskrll 461.1Sskrll#define IMX8MP_ICN_MEDIA 27 471.1Sskrll#define IMX8MP_ICM_LCDIF_RD 28 481.1Sskrll#define IMX8MP_ICM_LCDIF_WR 29 491.1Sskrll#define IMX8MP_ICM_ISI0 30 501.1Sskrll#define IMX8MP_ICM_ISI1 31 511.1Sskrll#define IMX8MP_ICM_ISI2 32 521.1Sskrll#define IMX8MP_ICM_ISP0 33 531.1Sskrll#define IMX8MP_ICM_ISP1 34 541.1Sskrll#define IMX8MP_ICM_DWE 35 551.1Sskrll 561.1Sskrll#define IMX8MP_ICN_VIDEO 36 571.1Sskrll#define IMX8MP_ICM_VPU_G1 37 581.1Sskrll#define IMX8MP_ICM_VPU_G2 38 591.1Sskrll#define IMX8MP_ICM_VPU_H1 39 601.1Sskrll 611.1Sskrll#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ 62