11.1Sskrll/* $NetBSD: qcom,qcs404.h,v 1.1.1.1 2020/01/03 14:33:03 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sskrll/* 51.1Sskrll * Qualcomm interconnect IDs 61.1Sskrll * 71.1Sskrll * Copyright (c) 2019, Linaro Ltd. 81.1Sskrll * Author: Georgi Djakov <georgi.djakov@linaro.org> 91.1Sskrll */ 101.1Sskrll 111.1Sskrll#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 121.1Sskrll#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 131.1Sskrll 141.1Sskrll#define MASTER_AMPSS_M0 0 151.1Sskrll#define MASTER_OXILI 1 161.1Sskrll#define MASTER_MDP_PORT0 2 171.1Sskrll#define MASTER_SNOC_BIMC_1 3 181.1Sskrll#define MASTER_TCU_0 4 191.1Sskrll#define SLAVE_EBI_CH0 5 201.1Sskrll#define SLAVE_BIMC_SNOC 6 211.1Sskrll 221.1Sskrll#define MASTER_SPDM 0 231.1Sskrll#define MASTER_BLSP_1 1 241.1Sskrll#define MASTER_BLSP_2 2 251.1Sskrll#define MASTER_XI_USB_HS1 3 261.1Sskrll#define MASTER_CRYPT0 4 271.1Sskrll#define MASTER_SDCC_1 5 281.1Sskrll#define MASTER_SDCC_2 6 291.1Sskrll#define MASTER_SNOC_PCNOC 7 301.1Sskrll#define MASTER_QPIC 8 311.1Sskrll#define PCNOC_INT_0 9 321.1Sskrll#define PCNOC_INT_2 10 331.1Sskrll#define PCNOC_INT_3 11 341.1Sskrll#define PCNOC_S_0 12 351.1Sskrll#define PCNOC_S_1 13 361.1Sskrll#define PCNOC_S_2 14 371.1Sskrll#define PCNOC_S_3 15 381.1Sskrll#define PCNOC_S_4 16 391.1Sskrll#define PCNOC_S_6 17 401.1Sskrll#define PCNOC_S_7 18 411.1Sskrll#define PCNOC_S_8 19 421.1Sskrll#define PCNOC_S_9 20 431.1Sskrll#define PCNOC_S_10 21 441.1Sskrll#define PCNOC_S_11 22 451.1Sskrll#define SLAVE_SPDM 23 461.1Sskrll#define SLAVE_PDM 24 471.1Sskrll#define SLAVE_PRNG 25 481.1Sskrll#define SLAVE_TCSR 26 491.1Sskrll#define SLAVE_SNOC_CFG 27 501.1Sskrll#define SLAVE_MESSAGE_RAM 28 511.1Sskrll#define SLAVE_DISP_SS_CFG 29 521.1Sskrll#define SLAVE_GPU_CFG 30 531.1Sskrll#define SLAVE_BLSP_1 31 541.1Sskrll#define SLAVE_BLSP_2 32 551.1Sskrll#define SLAVE_TLMM_NORTH 33 561.1Sskrll#define SLAVE_PCIE 34 571.1Sskrll#define SLAVE_ETHERNET 35 581.1Sskrll#define SLAVE_TLMM_EAST 36 591.1Sskrll#define SLAVE_TCU 37 601.1Sskrll#define SLAVE_PMIC_ARB 38 611.1Sskrll#define SLAVE_SDCC_1 39 621.1Sskrll#define SLAVE_SDCC_2 40 631.1Sskrll#define SLAVE_TLMM_SOUTH 41 641.1Sskrll#define SLAVE_USB_HS 42 651.1Sskrll#define SLAVE_USB3 43 661.1Sskrll#define SLAVE_CRYPTO_0_CFG 44 671.1Sskrll#define SLAVE_PCNOC_SNOC 45 681.1Sskrll 691.1Sskrll#define MASTER_QDSS_BAM 0 701.1Sskrll#define MASTER_BIMC_SNOC 1 711.1Sskrll#define MASTER_PCNOC_SNOC 2 721.1Sskrll#define MASTER_QDSS_ETR 3 731.1Sskrll#define MASTER_EMAC 4 741.1Sskrll#define MASTER_PCIE 5 751.1Sskrll#define MASTER_USB3 6 761.1Sskrll#define QDSS_INT 7 771.1Sskrll#define SNOC_INT_0 8 781.1Sskrll#define SNOC_INT_1 9 791.1Sskrll#define SNOC_INT_2 10 801.1Sskrll#define SLAVE_KPSS_AHB 11 811.1Sskrll#define SLAVE_WCSS 12 821.1Sskrll#define SLAVE_SNOC_BIMC_1 13 831.1Sskrll#define SLAVE_IMEM 14 841.1Sskrll#define SLAVE_SNOC_PCNOC 15 851.1Sskrll#define SLAVE_QDSS_STM 16 861.1Sskrll#define SLAVE_CATS_0 17 871.1Sskrll#define SLAVE_CATS_1 18 881.1Sskrll#define SLAVE_LPASS 19 891.1Sskrll 901.1Sskrll#endif 91