qcom,sdx55.h revision 1.1.1.1 
1/*	$NetBSD: qcom,sdx55.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * Qualcomm SDX55 interconnect IDs
6 *
7 * Copyright (c) 2021, Linaro Ltd.
8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
9 */
10
11#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H
12#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H
13
14#define MASTER_LLCC			0
15#define SLAVE_EBI_CH0			1
16
17#define MASTER_TCU_0			0
18#define MASTER_SNOC_GC_MEM_NOC		1
19#define MASTER_AMPSS_M0			2
20#define SLAVE_LLCC			3
21#define SLAVE_MEM_NOC_SNOC		4
22#define SLAVE_MEM_NOC_PCIE_SNOC		5
23
24#define MASTER_AUDIO			0
25#define MASTER_BLSP_1			1
26#define MASTER_QDSS_BAM			2
27#define MASTER_QPIC			3
28#define MASTER_SNOC_CFG			4
29#define MASTER_SPMI_FETCHER		5
30#define MASTER_ANOC_SNOC		6
31#define MASTER_IPA			7
32#define MASTER_MEM_NOC_SNOC		8
33#define MASTER_MEM_NOC_PCIE_SNOC	9
34#define MASTER_CRYPTO_CORE_0		10
35#define MASTER_EMAC			11
36#define MASTER_IPA_PCIE			12
37#define MASTER_PCIE			13
38#define MASTER_QDSS_ETR			14
39#define MASTER_SDCC_1			15
40#define MASTER_USB3			16
41#define SLAVE_AOP			17
42#define SLAVE_AOSS			18
43#define SLAVE_APPSS			19
44#define SLAVE_AUDIO			20
45#define SLAVE_BLSP_1			21
46#define SLAVE_CLK_CTL			22
47#define SLAVE_CRYPTO_0_CFG		23
48#define SLAVE_CNOC_DDRSS		24
49#define SLAVE_ECC_CFG			25
50#define SLAVE_EMAC_CFG			26
51#define SLAVE_IMEM_CFG			27
52#define SLAVE_IPA_CFG			28
53#define SLAVE_CNOC_MSS			29
54#define SLAVE_PCIE_PARF			30
55#define SLAVE_PDM			31
56#define SLAVE_PRNG			32
57#define SLAVE_QDSS_CFG			33
58#define SLAVE_QPIC			34
59#define SLAVE_SDCC_1			35
60#define SLAVE_SNOC_CFG			36
61#define SLAVE_SPMI_FETCHER		37
62#define SLAVE_SPMI_VGI_COEX		38
63#define SLAVE_TCSR			39
64#define SLAVE_TLMM			40
65#define SLAVE_USB3			41
66#define SLAVE_USB3_PHY_CFG		42
67#define SLAVE_ANOC_SNOC			43
68#define SLAVE_SNOC_MEM_NOC_GC		44
69#define SLAVE_OCIMEM			45
70#define SLAVE_SERVICE_SNOC		46
71#define SLAVE_PCIE_0			47
72#define SLAVE_QDSS_STM			48
73#define SLAVE_TCU			49
74
75#define MASTER_IPA_CORE			0
76#define SLAVE_IPA_CORE			1
77
78#endif
79