1 1.1 jmcneill /* $NetBSD: tegra210-mc.h,v 1.1.1.4 2021/11/07 16:49:56 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H 5 1.1 jmcneill #define DT_BINDINGS_MEMORY_TEGRA210_MC_H 6 1.1 jmcneill 7 1.1 jmcneill #define TEGRA_SWGROUP_PTC 0 8 1.1 jmcneill #define TEGRA_SWGROUP_DC 1 9 1.1 jmcneill #define TEGRA_SWGROUP_DCB 2 10 1.1 jmcneill #define TEGRA_SWGROUP_AFI 3 11 1.1 jmcneill #define TEGRA_SWGROUP_AVPC 4 12 1.1 jmcneill #define TEGRA_SWGROUP_HDA 5 13 1.1 jmcneill #define TEGRA_SWGROUP_HC 6 14 1.1 jmcneill #define TEGRA_SWGROUP_NVENC 7 15 1.1 jmcneill #define TEGRA_SWGROUP_PPCS 8 16 1.1 jmcneill #define TEGRA_SWGROUP_SATA 9 17 1.1 jmcneill #define TEGRA_SWGROUP_MPCORE 10 18 1.1 jmcneill #define TEGRA_SWGROUP_ISP2 11 19 1.1 jmcneill #define TEGRA_SWGROUP_XUSB_HOST 12 20 1.1 jmcneill #define TEGRA_SWGROUP_XUSB_DEV 13 21 1.1 jmcneill #define TEGRA_SWGROUP_ISP2B 14 22 1.1 jmcneill #define TEGRA_SWGROUP_TSEC 15 23 1.1 jmcneill #define TEGRA_SWGROUP_A9AVP 16 24 1.1 jmcneill #define TEGRA_SWGROUP_GPU 17 25 1.1 jmcneill #define TEGRA_SWGROUP_SDMMC1A 18 26 1.1 jmcneill #define TEGRA_SWGROUP_SDMMC2A 19 27 1.1 jmcneill #define TEGRA_SWGROUP_SDMMC3A 20 28 1.1 jmcneill #define TEGRA_SWGROUP_SDMMC4A 21 29 1.1 jmcneill #define TEGRA_SWGROUP_VIC 22 30 1.1 jmcneill #define TEGRA_SWGROUP_VI 23 31 1.1 jmcneill #define TEGRA_SWGROUP_NVDEC 24 32 1.1 jmcneill #define TEGRA_SWGROUP_APE 25 33 1.1 jmcneill #define TEGRA_SWGROUP_NVJPG 26 34 1.1 jmcneill #define TEGRA_SWGROUP_SE 27 35 1.1 jmcneill #define TEGRA_SWGROUP_AXIAP 28 36 1.1 jmcneill #define TEGRA_SWGROUP_ETR 29 37 1.1 jmcneill #define TEGRA_SWGROUP_TSECB 30 38 1.1.1.4 jmcneill #define TEGRA_SWGROUP_NV 31 39 1.1.1.4 jmcneill #define TEGRA_SWGROUP_NV2 32 40 1.1.1.4 jmcneill #define TEGRA_SWGROUP_PPCS1 33 41 1.1.1.4 jmcneill #define TEGRA_SWGROUP_DC1 34 42 1.1.1.4 jmcneill #define TEGRA_SWGROUP_PPCS2 35 43 1.1.1.4 jmcneill #define TEGRA_SWGROUP_HC1 36 44 1.1.1.4 jmcneill #define TEGRA_SWGROUP_SE1 37 45 1.1.1.4 jmcneill #define TEGRA_SWGROUP_TSEC1 38 46 1.1.1.4 jmcneill #define TEGRA_SWGROUP_TSECB1 39 47 1.1.1.4 jmcneill #define TEGRA_SWGROUP_NVDEC1 40 48 1.1 jmcneill 49 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_AFI 0 50 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_AVPC 1 51 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_DC 2 52 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_DCB 3 53 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_HC 4 54 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_HDA 5 55 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_ISP2 6 56 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_MPCORE 7 57 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_NVENC 8 58 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_PPCS 9 59 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SATA 10 60 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_VI 11 61 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_VIC 12 62 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_XUSB_HOST 13 63 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_XUSB_DEV 14 64 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_A9AVP 15 65 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_TSEC 16 66 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SDMMC1 17 67 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SDMMC2 18 68 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SDMMC3 19 69 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SDMMC4 20 70 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_ISP2B 21 71 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_GPU 22 72 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_NVDEC 23 73 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_APE 24 74 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_SE 25 75 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_NVJPG 26 76 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_AXIAP 27 77 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_ETR 28 78 1.1.1.3 jmcneill #define TEGRA210_MC_RESET_TSECB 29 79 1.1.1.3 jmcneill 80 1.1 jmcneill #endif 81