1 1.1 jmcneill /* $NetBSD: stm32f4-rcc.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * This header provides constants for the STM32F4 RCC IP 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H 9 1.1 jmcneill #define _DT_BINDINGS_MFD_STM32F4_RCC_H 10 1.1 jmcneill 11 1.1 jmcneill /* AHB1 */ 12 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOA 0 13 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOB 1 14 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOC 2 15 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOD 3 16 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOE 4 17 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOF 5 18 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOG 6 19 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOH 7 20 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOI 8 21 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOJ 9 22 1.1 jmcneill #define STM32F4_RCC_AHB1_GPIOK 10 23 1.1 jmcneill #define STM32F4_RCC_AHB1_CRC 12 24 1.1 jmcneill #define STM32F4_RCC_AHB1_BKPSRAM 18 25 1.1 jmcneill #define STM32F4_RCC_AHB1_CCMDATARAM 20 26 1.1 jmcneill #define STM32F4_RCC_AHB1_DMA1 21 27 1.1 jmcneill #define STM32F4_RCC_AHB1_DMA2 22 28 1.1 jmcneill #define STM32F4_RCC_AHB1_DMA2D 23 29 1.1 jmcneill #define STM32F4_RCC_AHB1_ETHMAC 25 30 1.1 jmcneill #define STM32F4_RCC_AHB1_ETHMACTX 26 31 1.1 jmcneill #define STM32F4_RCC_AHB1_ETHMACRX 27 32 1.1 jmcneill #define STM32F4_RCC_AHB1_ETHMACPTP 28 33 1.1 jmcneill #define STM32F4_RCC_AHB1_OTGHS 29 34 1.1 jmcneill #define STM32F4_RCC_AHB1_OTGHSULPI 30 35 1.1 jmcneill 36 1.1 jmcneill #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) 37 1.1 jmcneill #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) 38 1.1 jmcneill 39 1.1 jmcneill 40 1.1 jmcneill /* AHB2 */ 41 1.1 jmcneill #define STM32F4_RCC_AHB2_DCMI 0 42 1.1 jmcneill #define STM32F4_RCC_AHB2_CRYP 4 43 1.1 jmcneill #define STM32F4_RCC_AHB2_HASH 5 44 1.1 jmcneill #define STM32F4_RCC_AHB2_RNG 6 45 1.1 jmcneill #define STM32F4_RCC_AHB2_OTGFS 7 46 1.1 jmcneill 47 1.1 jmcneill #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) 48 1.1 jmcneill #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) 49 1.1 jmcneill 50 1.1 jmcneill /* AHB3 */ 51 1.1 jmcneill #define STM32F4_RCC_AHB3_FMC 0 52 1.1 jmcneill #define STM32F4_RCC_AHB3_QSPI 1 53 1.1 jmcneill 54 1.1 jmcneill #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) 55 1.1 jmcneill #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) 56 1.1 jmcneill 57 1.1 jmcneill /* APB1 */ 58 1.1 jmcneill #define STM32F4_RCC_APB1_TIM2 0 59 1.1 jmcneill #define STM32F4_RCC_APB1_TIM3 1 60 1.1 jmcneill #define STM32F4_RCC_APB1_TIM4 2 61 1.1 jmcneill #define STM32F4_RCC_APB1_TIM5 3 62 1.1 jmcneill #define STM32F4_RCC_APB1_TIM6 4 63 1.1 jmcneill #define STM32F4_RCC_APB1_TIM7 5 64 1.1 jmcneill #define STM32F4_RCC_APB1_TIM12 6 65 1.1 jmcneill #define STM32F4_RCC_APB1_TIM13 7 66 1.1 jmcneill #define STM32F4_RCC_APB1_TIM14 8 67 1.1 jmcneill #define STM32F4_RCC_APB1_WWDG 11 68 1.1 jmcneill #define STM32F4_RCC_APB1_SPI2 14 69 1.1 jmcneill #define STM32F4_RCC_APB1_SPI3 15 70 1.1 jmcneill #define STM32F4_RCC_APB1_UART2 17 71 1.1 jmcneill #define STM32F4_RCC_APB1_UART3 18 72 1.1 jmcneill #define STM32F4_RCC_APB1_UART4 19 73 1.1 jmcneill #define STM32F4_RCC_APB1_UART5 20 74 1.1 jmcneill #define STM32F4_RCC_APB1_I2C1 21 75 1.1 jmcneill #define STM32F4_RCC_APB1_I2C2 22 76 1.1 jmcneill #define STM32F4_RCC_APB1_I2C3 23 77 1.1 jmcneill #define STM32F4_RCC_APB1_CAN1 25 78 1.1 jmcneill #define STM32F4_RCC_APB1_CAN2 26 79 1.1 jmcneill #define STM32F4_RCC_APB1_PWR 28 80 1.1 jmcneill #define STM32F4_RCC_APB1_DAC 29 81 1.1 jmcneill #define STM32F4_RCC_APB1_UART7 30 82 1.1 jmcneill #define STM32F4_RCC_APB1_UART8 31 83 1.1 jmcneill 84 1.1 jmcneill #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) 85 1.1 jmcneill #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) 86 1.1 jmcneill 87 1.1 jmcneill /* APB2 */ 88 1.1 jmcneill #define STM32F4_RCC_APB2_TIM1 0 89 1.1 jmcneill #define STM32F4_RCC_APB2_TIM8 1 90 1.1 jmcneill #define STM32F4_RCC_APB2_USART1 4 91 1.1 jmcneill #define STM32F4_RCC_APB2_USART6 5 92 1.1 jmcneill #define STM32F4_RCC_APB2_ADC1 8 93 1.1 jmcneill #define STM32F4_RCC_APB2_ADC2 9 94 1.1 jmcneill #define STM32F4_RCC_APB2_ADC3 10 95 1.1 jmcneill #define STM32F4_RCC_APB2_SDIO 11 96 1.1 jmcneill #define STM32F4_RCC_APB2_SPI1 12 97 1.1 jmcneill #define STM32F4_RCC_APB2_SPI4 13 98 1.1 jmcneill #define STM32F4_RCC_APB2_SYSCFG 14 99 1.1 jmcneill #define STM32F4_RCC_APB2_TIM9 16 100 1.1 jmcneill #define STM32F4_RCC_APB2_TIM10 17 101 1.1 jmcneill #define STM32F4_RCC_APB2_TIM11 18 102 1.1 jmcneill #define STM32F4_RCC_APB2_SPI5 20 103 1.1 jmcneill #define STM32F4_RCC_APB2_SPI6 21 104 1.1 jmcneill #define STM32F4_RCC_APB2_SAI1 22 105 1.1 jmcneill #define STM32F4_RCC_APB2_LTDC 26 106 1.1 jmcneill #define STM32F4_RCC_APB2_DSI 27 107 1.1 jmcneill 108 1.1 jmcneill #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) 109 1.1 jmcneill #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) 110 1.1 jmcneill 111 1.1 jmcneill #endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ 112