1 1.1 jmcneill /* $NetBSD: ti-dp83867.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 1.1 jmcneill 3 1.1.1.3 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Device Tree constants for the Texas Instruments DP83867 PHY 6 1.1 jmcneill * 7 1.1 jmcneill * Author: Dan Murphy <dmurphy (at) ti.com> 8 1.1 jmcneill * 9 1.1 jmcneill * Copyright: (C) 2015 Texas Instruments, Inc. 10 1.1 jmcneill */ 11 1.1 jmcneill 12 1.1 jmcneill #ifndef _DT_BINDINGS_TI_DP83867_H 13 1.1 jmcneill #define _DT_BINDINGS_TI_DP83867_H 14 1.1 jmcneill 15 1.1 jmcneill /* PHY CTRL bits */ 16 1.1 jmcneill #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 17 1.1 jmcneill #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 18 1.1 jmcneill #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 19 1.1 jmcneill #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 20 1.1 jmcneill 21 1.1 jmcneill /* RGMIIDCTL internal delay for rx and tx */ 22 1.1 jmcneill #define DP83867_RGMIIDCTL_250_PS 0x0 23 1.1 jmcneill #define DP83867_RGMIIDCTL_500_PS 0x1 24 1.1 jmcneill #define DP83867_RGMIIDCTL_750_PS 0x2 25 1.1 jmcneill #define DP83867_RGMIIDCTL_1_NS 0x3 26 1.1 jmcneill #define DP83867_RGMIIDCTL_1_25_NS 0x4 27 1.1 jmcneill #define DP83867_RGMIIDCTL_1_50_NS 0x5 28 1.1 jmcneill #define DP83867_RGMIIDCTL_1_75_NS 0x6 29 1.1 jmcneill #define DP83867_RGMIIDCTL_2_00_NS 0x7 30 1.1 jmcneill #define DP83867_RGMIIDCTL_2_25_NS 0x8 31 1.1 jmcneill #define DP83867_RGMIIDCTL_2_50_NS 0x9 32 1.1 jmcneill #define DP83867_RGMIIDCTL_2_75_NS 0xa 33 1.1 jmcneill #define DP83867_RGMIIDCTL_3_00_NS 0xb 34 1.1 jmcneill #define DP83867_RGMIIDCTL_3_25_NS 0xc 35 1.1 jmcneill #define DP83867_RGMIIDCTL_3_50_NS 0xd 36 1.1 jmcneill #define DP83867_RGMIIDCTL_3_75_NS 0xe 37 1.1 jmcneill #define DP83867_RGMIIDCTL_4_00_NS 0xf 38 1.1 jmcneill 39 1.1.1.2 jmcneill /* IO_MUX_CFG - Clock output selection */ 40 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 41 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 42 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 43 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 44 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 45 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 46 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 47 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 48 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 49 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 50 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 51 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 52 1.1.1.2 jmcneill #define DP83867_CLK_O_SEL_REF_CLK 0xC 53 1.1.1.3 skrll /* Special flag to indicate clock should be off */ 54 1.1.1.3 skrll #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 55 1.1 jmcneill #endif 56
Indexes created Tue Oct 07 11:09:55 GMT 2025