1 1.1 skrll /* $NetBSD: ti-dp83869.h,v 1.1.1.1 2020/01/03 14:33:04 skrll Exp $ */ 2 1.1 skrll 3 1.1 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 skrll /* 5 1.1 skrll * Device Tree constants for the Texas Instruments DP83869 PHY 6 1.1 skrll * 7 1.1 skrll * Author: Dan Murphy <dmurphy (at) ti.com> 8 1.1 skrll * 9 1.1 skrll * Copyright: (C) 2019 Texas Instruments, Inc. 10 1.1 skrll */ 11 1.1 skrll 12 1.1 skrll #ifndef _DT_BINDINGS_TI_DP83869_H 13 1.1 skrll #define _DT_BINDINGS_TI_DP83869_H 14 1.1 skrll 15 1.1 skrll /* PHY CTRL bits */ 16 1.1 skrll #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 17 1.1 skrll #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 18 1.1 skrll #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 19 1.1 skrll #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 20 1.1 skrll 21 1.1 skrll /* IO_MUX_CFG - Clock output selection */ 22 1.1 skrll #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 23 1.1 skrll #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 24 1.1 skrll #define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 25 1.1 skrll #define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 26 1.1 skrll #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 27 1.1 skrll #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 28 1.1 skrll #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 29 1.1 skrll #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 30 1.1 skrll #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 31 1.1 skrll #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 32 1.1 skrll #define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa 33 1.1 skrll #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb 34 1.1 skrll #define DP83869_CLK_O_SEL_REF_CLK 0xc 35 1.1 skrll 36 1.1 skrll #define DP83869_RGMII_COPPER_ETHERNET 0x00 37 1.1 skrll #define DP83869_RGMII_1000_BASE 0x01 38 1.1 skrll #define DP83869_RGMII_100_BASE 0x02 39 1.1 skrll #define DP83869_RGMII_SGMII_BRIDGE 0x03 40 1.1 skrll #define DP83869_1000M_MEDIA_CONVERT 0x04 41 1.1 skrll #define DP83869_100M_MEDIA_CONVERT 0x05 42 1.1 skrll #define DP83869_SGMII_COPPER_ETHERNET 0x06 43 1.1 skrll 44 1.1 skrll #endif 45
Indexes created Tue Oct 07 11:09:55 GMT 2025