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      1      1.1  jmcneill /*	$NetBSD: pinctrl-tegra.h,v 1.1.1.2 2020/01/03 14:33:03 skrll Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.2     skrll /* SPDX-License-Identifier: GPL-2.0-only */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * This header provides constants for Tegra pinctrl bindings.
      6      1.1  jmcneill  *
      7      1.1  jmcneill  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
      8      1.1  jmcneill  *
      9      1.1  jmcneill  * Author: Laxman Dewangan <ldewangan (at) nvidia.com>
     10      1.1  jmcneill  */
     11      1.1  jmcneill 
     12      1.1  jmcneill #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
     13      1.1  jmcneill #define _DT_BINDINGS_PINCTRL_TEGRA_H
     14      1.1  jmcneill 
     15      1.1  jmcneill /*
     16      1.1  jmcneill  * Enable/disable for diffeent dt properties. This is applicable for
     17      1.1  jmcneill  * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
     18      1.1  jmcneill  * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
     19      1.1  jmcneill  */
     20      1.1  jmcneill #define TEGRA_PIN_DISABLE				0
     21      1.1  jmcneill #define TEGRA_PIN_ENABLE				1
     22      1.1  jmcneill 
     23      1.1  jmcneill #define TEGRA_PIN_PULL_NONE				0
     24      1.1  jmcneill #define TEGRA_PIN_PULL_DOWN				1
     25      1.1  jmcneill #define TEGRA_PIN_PULL_UP				2
     26      1.1  jmcneill 
     27      1.1  jmcneill /* Low power mode driver */
     28      1.1  jmcneill #define TEGRA_PIN_LP_DRIVE_DIV_8			0
     29      1.1  jmcneill #define TEGRA_PIN_LP_DRIVE_DIV_4			1
     30      1.1  jmcneill #define TEGRA_PIN_LP_DRIVE_DIV_2			2
     31      1.1  jmcneill #define TEGRA_PIN_LP_DRIVE_DIV_1			3
     32      1.1  jmcneill 
     33      1.1  jmcneill /* Rising/Falling slew rate */
     34      1.1  jmcneill #define TEGRA_PIN_SLEW_RATE_FASTEST			0
     35      1.1  jmcneill #define TEGRA_PIN_SLEW_RATE_FAST			1
     36      1.1  jmcneill #define TEGRA_PIN_SLEW_RATE_SLOW			2
     37      1.1  jmcneill #define TEGRA_PIN_SLEW_RATE_SLOWEST			3
     38      1.1  jmcneill 
     39      1.1  jmcneill #endif
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