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      1  1.1  jmcneill /*	$NetBSD: pinctrl-zynqmp.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4  1.1  jmcneill /*
      5  1.1  jmcneill  * MIO pin configuration defines for Xilinx ZynqMP
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Copyright (C) 2020 Xilinx, Inc.
      8  1.1  jmcneill  */
      9  1.1  jmcneill 
     10  1.1  jmcneill #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
     11  1.1  jmcneill #define _DT_BINDINGS_PINCTRL_ZYNQMP_H
     12  1.1  jmcneill 
     13  1.1  jmcneill /* Bit value for different voltage levels */
     14  1.1  jmcneill #define IO_STANDARD_LVCMOS33	0
     15  1.1  jmcneill #define IO_STANDARD_LVCMOS18	1
     16  1.1  jmcneill 
     17  1.1  jmcneill /* Bit values for Slew Rates */
     18  1.1  jmcneill #define SLEW_RATE_FAST		0
     19  1.1  jmcneill #define SLEW_RATE_SLOW		1
     20  1.1  jmcneill 
     21  1.1  jmcneill #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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