1 1.1 jmcneill /* $NetBSD: samsung.h,v 1.1.1.3 2019/01/22 14:57:01 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1.1.3 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Samsung's Exynos pinctrl bindings 6 1.1 jmcneill * 7 1.1 jmcneill * Copyright (c) 2016 Samsung Electronics Co., Ltd. 8 1.1 jmcneill * http://www.samsung.com 9 1.1 jmcneill * Author: Krzysztof Kozlowski <krzk (at) kernel.org> 10 1.1.1.3 jmcneill */ 11 1.1 jmcneill 12 1.1 jmcneill #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 13 1.1 jmcneill #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 14 1.1 jmcneill 15 1.1 jmcneill #define EXYNOS_PIN_PULL_NONE 0 16 1.1 jmcneill #define EXYNOS_PIN_PULL_DOWN 1 17 1.1 jmcneill #define EXYNOS_PIN_PULL_UP 3 18 1.1 jmcneill 19 1.1 jmcneill #define S3C64XX_PIN_PULL_NONE 0 20 1.1 jmcneill #define S3C64XX_PIN_PULL_DOWN 1 21 1.1 jmcneill #define S3C64XX_PIN_PULL_UP 2 22 1.1 jmcneill 23 1.1 jmcneill /* Pin function in power down mode */ 24 1.1 jmcneill #define EXYNOS_PIN_PDN_OUT0 0 25 1.1 jmcneill #define EXYNOS_PIN_PDN_OUT1 1 26 1.1 jmcneill #define EXYNOS_PIN_PDN_INPUT 2 27 1.1 jmcneill #define EXYNOS_PIN_PDN_PREV 3 28 1.1 jmcneill 29 1.1 jmcneill /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 30 1.1 jmcneill #define EXYNOS4_PIN_DRV_LV1 0 31 1.1 jmcneill #define EXYNOS4_PIN_DRV_LV2 2 32 1.1 jmcneill #define EXYNOS4_PIN_DRV_LV3 1 33 1.1 jmcneill #define EXYNOS4_PIN_DRV_LV4 3 34 1.1 jmcneill 35 1.1 jmcneill /* Drive strengths for Exynos5260 */ 36 1.1 jmcneill #define EXYNOS5260_PIN_DRV_LV1 0 37 1.1 jmcneill #define EXYNOS5260_PIN_DRV_LV2 1 38 1.1 jmcneill #define EXYNOS5260_PIN_DRV_LV4 2 39 1.1 jmcneill #define EXYNOS5260_PIN_DRV_LV6 3 40 1.1 jmcneill 41 1.1 jmcneill /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ 42 1.1 jmcneill #define EXYNOS5420_PIN_DRV_LV1 0 43 1.1 jmcneill #define EXYNOS5420_PIN_DRV_LV2 1 44 1.1 jmcneill #define EXYNOS5420_PIN_DRV_LV3 2 45 1.1 jmcneill #define EXYNOS5420_PIN_DRV_LV4 3 46 1.1 jmcneill 47 1.1 jmcneill /* Drive strengths for Exynos5433 */ 48 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR1 0 49 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR2 1 50 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR3 2 51 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR4 3 52 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR5 4 53 1.1 jmcneill #define EXYNOS5433_PIN_DRV_FAST_SR6 5 54 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 55 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 56 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 57 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 58 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 59 1.1 jmcneill #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 60 1.1 jmcneill 61 1.1 jmcneill #define EXYNOS_PIN_FUNC_INPUT 0 62 1.1 jmcneill #define EXYNOS_PIN_FUNC_OUTPUT 1 63 1.1 jmcneill #define EXYNOS_PIN_FUNC_2 2 64 1.1 jmcneill #define EXYNOS_PIN_FUNC_3 3 65 1.1 jmcneill #define EXYNOS_PIN_FUNC_4 4 66 1.1 jmcneill #define EXYNOS_PIN_FUNC_5 5 67 1.1 jmcneill #define EXYNOS_PIN_FUNC_6 6 68 1.1.1.2 jmcneill #define EXYNOS_PIN_FUNC_EINT 0xf 69 1.1.1.2 jmcneill #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 70 1.1 jmcneill 71 1.1 jmcneill /* Drive strengths for Exynos7 FSYS1 block */ 72 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 73 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 74 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 75 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 76 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 77 1.1 jmcneill #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 78 1.1 jmcneill 79 1.1 jmcneill #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ 80
Indexes created Wed Oct 01 15:09:59 GMT 2025