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samsung.h revision 1.1.1.1.4.2
      1 /*	$NetBSD: samsung.h,v 1.1.1.1.4.2 2017/07/18 16:08:59 snj Exp $	*/
      2 
      3 /*
      4  * Samsung's Exynos pinctrl bindings
      5  *
      6  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
      7  *		http://www.samsung.com
      8  * Author: Krzysztof Kozlowski <krzk (at) kernel.org>
      9  *
     10  * This program is free software; you can redistribute it and/or modify
     11  * it under the terms of the GNU General Public License version 2 as
     12  * published by the Free Software Foundation.
     13 */
     14 
     15 #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
     16 #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
     17 
     18 #define EXYNOS_PIN_PULL_NONE		0
     19 #define EXYNOS_PIN_PULL_DOWN		1
     20 #define EXYNOS_PIN_PULL_UP		3
     21 
     22 #define S3C64XX_PIN_PULL_NONE		0
     23 #define S3C64XX_PIN_PULL_DOWN		1
     24 #define S3C64XX_PIN_PULL_UP		2
     25 
     26 /* Pin function in power down mode */
     27 #define EXYNOS_PIN_PDN_OUT0		0
     28 #define EXYNOS_PIN_PDN_OUT1		1
     29 #define EXYNOS_PIN_PDN_INPUT		2
     30 #define EXYNOS_PIN_PDN_PREV		3
     31 
     32 /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
     33 #define EXYNOS4_PIN_DRV_LV1		0
     34 #define EXYNOS4_PIN_DRV_LV2		2
     35 #define EXYNOS4_PIN_DRV_LV3		1
     36 #define EXYNOS4_PIN_DRV_LV4		3
     37 
     38 /* Drive strengths for Exynos5260 */
     39 #define EXYNOS5260_PIN_DRV_LV1		0
     40 #define EXYNOS5260_PIN_DRV_LV2		1
     41 #define EXYNOS5260_PIN_DRV_LV4		2
     42 #define EXYNOS5260_PIN_DRV_LV6		3
     43 
     44 /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */
     45 #define EXYNOS5420_PIN_DRV_LV1		0
     46 #define EXYNOS5420_PIN_DRV_LV2		1
     47 #define EXYNOS5420_PIN_DRV_LV3		2
     48 #define EXYNOS5420_PIN_DRV_LV4		3
     49 
     50 /* Drive strengths for Exynos5433 */
     51 #define EXYNOS5433_PIN_DRV_FAST_SR1	0
     52 #define EXYNOS5433_PIN_DRV_FAST_SR2	1
     53 #define EXYNOS5433_PIN_DRV_FAST_SR3	2
     54 #define EXYNOS5433_PIN_DRV_FAST_SR4	3
     55 #define EXYNOS5433_PIN_DRV_FAST_SR5	4
     56 #define EXYNOS5433_PIN_DRV_FAST_SR6	5
     57 #define EXYNOS5433_PIN_DRV_SLOW_SR1	8
     58 #define EXYNOS5433_PIN_DRV_SLOW_SR2	9
     59 #define EXYNOS5433_PIN_DRV_SLOW_SR3	0xa
     60 #define EXYNOS5433_PIN_DRV_SLOW_SR4	0xb
     61 #define EXYNOS5433_PIN_DRV_SLOW_SR5	0xc
     62 #define EXYNOS5433_PIN_DRV_SLOW_SR6	0xf
     63 
     64 #define EXYNOS_PIN_FUNC_INPUT		0
     65 #define EXYNOS_PIN_FUNC_OUTPUT		1
     66 #define EXYNOS_PIN_FUNC_2		2
     67 #define EXYNOS_PIN_FUNC_3		3
     68 #define EXYNOS_PIN_FUNC_4		4
     69 #define EXYNOS_PIN_FUNC_5		5
     70 #define EXYNOS_PIN_FUNC_6		6
     71 #define EXYNOS_PIN_FUNC_F		0xf
     72 
     73 /* Drive strengths for Exynos7 FSYS1 block */
     74 #define EXYNOS7_FSYS1_PIN_DRV_LV1	0
     75 #define EXYNOS7_FSYS1_PIN_DRV_LV2	4
     76 #define EXYNOS7_FSYS1_PIN_DRV_LV3	2
     77 #define EXYNOS7_FSYS1_PIN_DRV_LV4	6
     78 #define EXYNOS7_FSYS1_PIN_DRV_LV5	1
     79 #define EXYNOS7_FSYS1_PIN_DRV_LV6	5
     80 
     81 #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
     82