11.1Sskrll/* $NetBSD: sppctl-sp7021.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 41.1Sskrll/* 51.1Sskrll * Sunplus SP7021 dt-bindings Pinctrl header file 61.1Sskrll * Copyright (C) Sunplus Tech/Tibbo Tech. 71.1Sskrll * Author: Dvorkin Dmitry <dvorkin@tibbo.com> 81.1Sskrll */ 91.1Sskrll 101.1Sskrll#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 111.1Sskrll#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 121.1Sskrll 131.1Sskrll#include <dt-bindings/pinctrl/sppctl.h> 141.1Sskrll 151.1Sskrll/* 161.1Sskrll * Please don't change the order of the following defines. 171.1Sskrll * They are based on order of 'hardware' control register 181.1Sskrll * defined in MOON2 ~ MOON3 registers. 191.1Sskrll */ 201.1Sskrll#define MUXF_GPIO 0 211.1Sskrll#define MUXF_IOP 1 221.1Sskrll#define MUXF_L2SW_CLK_OUT 2 231.1Sskrll#define MUXF_L2SW_MAC_SMI_MDC 3 241.1Sskrll#define MUXF_L2SW_LED_FLASH0 4 251.1Sskrll#define MUXF_L2SW_LED_FLASH1 5 261.1Sskrll#define MUXF_L2SW_LED_ON0 6 271.1Sskrll#define MUXF_L2SW_LED_ON1 7 281.1Sskrll#define MUXF_L2SW_MAC_SMI_MDIO 8 291.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_TXEN 9 301.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_TXD0 10 311.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_TXD1 11 321.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 331.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_RXD0 13 341.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_RXD1 14 351.1Sskrll#define MUXF_L2SW_P0_MAC_RMII_RXER 15 361.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_TXEN 16 371.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_TXD0 17 381.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_TXD1 18 391.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 401.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_RXD0 20 411.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_RXD1 21 421.1Sskrll#define MUXF_L2SW_P1_MAC_RMII_RXER 22 431.1Sskrll#define MUXF_DAISY_MODE 23 441.1Sskrll#define MUXF_SDIO_CLK 24 451.1Sskrll#define MUXF_SDIO_CMD 25 461.1Sskrll#define MUXF_SDIO_D0 26 471.1Sskrll#define MUXF_SDIO_D1 27 481.1Sskrll#define MUXF_SDIO_D2 28 491.1Sskrll#define MUXF_SDIO_D3 29 501.1Sskrll#define MUXF_PWM0 30 511.1Sskrll#define MUXF_PWM1 31 521.1Sskrll#define MUXF_PWM2 32 531.1Sskrll#define MUXF_PWM3 33 541.1Sskrll#define MUXF_PWM4 34 551.1Sskrll#define MUXF_PWM5 35 561.1Sskrll#define MUXF_PWM6 36 571.1Sskrll#define MUXF_PWM7 37 581.1Sskrll#define MUXF_ICM0_D 38 591.1Sskrll#define MUXF_ICM1_D 39 601.1Sskrll#define MUXF_ICM2_D 40 611.1Sskrll#define MUXF_ICM3_D 41 621.1Sskrll#define MUXF_ICM0_CLK 42 631.1Sskrll#define MUXF_ICM1_CLK 43 641.1Sskrll#define MUXF_ICM2_CLK 44 651.1Sskrll#define MUXF_ICM3_CLK 45 661.1Sskrll#define MUXF_SPIM0_INT 46 671.1Sskrll#define MUXF_SPIM0_CLK 47 681.1Sskrll#define MUXF_SPIM0_EN 48 691.1Sskrll#define MUXF_SPIM0_DO 49 701.1Sskrll#define MUXF_SPIM0_DI 50 711.1Sskrll#define MUXF_SPIM1_INT 51 721.1Sskrll#define MUXF_SPIM1_CLK 52 731.1Sskrll#define MUXF_SPIM1_EN 53 741.1Sskrll#define MUXF_SPIM1_DO 54 751.1Sskrll#define MUXF_SPIM1_DI 55 761.1Sskrll#define MUXF_SPIM2_INT 56 771.1Sskrll#define MUXF_SPIM2_CLK 57 781.1Sskrll#define MUXF_SPIM2_EN 58 791.1Sskrll#define MUXF_SPIM2_DO 59 801.1Sskrll#define MUXF_SPIM2_DI 60 811.1Sskrll#define MUXF_SPIM3_INT 61 821.1Sskrll#define MUXF_SPIM3_CLK 62 831.1Sskrll#define MUXF_SPIM3_EN 63 841.1Sskrll#define MUXF_SPIM3_DO 64 851.1Sskrll#define MUXF_SPIM3_DI 65 861.1Sskrll#define MUXF_SPI0S_INT 66 871.1Sskrll#define MUXF_SPI0S_CLK 67 881.1Sskrll#define MUXF_SPI0S_EN 68 891.1Sskrll#define MUXF_SPI0S_DO 69 901.1Sskrll#define MUXF_SPI0S_DI 70 911.1Sskrll#define MUXF_SPI1S_INT 71 921.1Sskrll#define MUXF_SPI1S_CLK 72 931.1Sskrll#define MUXF_SPI1S_EN 73 941.1Sskrll#define MUXF_SPI1S_DO 74 951.1Sskrll#define MUXF_SPI1S_DI 75 961.1Sskrll#define MUXF_SPI2S_INT 76 971.1Sskrll#define MUXF_SPI2S_CLK 77 981.1Sskrll#define MUXF_SPI2S_EN 78 991.1Sskrll#define MUXF_SPI2S_DO 79 1001.1Sskrll#define MUXF_SPI2S_DI 80 1011.1Sskrll#define MUXF_SPI3S_INT 81 1021.1Sskrll#define MUXF_SPI3S_CLK 82 1031.1Sskrll#define MUXF_SPI3S_EN 83 1041.1Sskrll#define MUXF_SPI3S_DO 84 1051.1Sskrll#define MUXF_SPI3S_DI 85 1061.1Sskrll#define MUXF_I2CM0_CLK 86 1071.1Sskrll#define MUXF_I2CM0_DAT 87 1081.1Sskrll#define MUXF_I2CM1_CLK 88 1091.1Sskrll#define MUXF_I2CM1_DAT 89 1101.1Sskrll#define MUXF_I2CM2_CLK 90 1111.1Sskrll#define MUXF_I2CM2_DAT 91 1121.1Sskrll#define MUXF_I2CM3_CLK 92 1131.1Sskrll#define MUXF_I2CM3_DAT 93 1141.1Sskrll#define MUXF_UA1_TX 94 1151.1Sskrll#define MUXF_UA1_RX 95 1161.1Sskrll#define MUXF_UA1_CTS 96 1171.1Sskrll#define MUXF_UA1_RTS 97 1181.1Sskrll#define MUXF_UA2_TX 98 1191.1Sskrll#define MUXF_UA2_RX 99 1201.1Sskrll#define MUXF_UA2_CTS 100 1211.1Sskrll#define MUXF_UA2_RTS 101 1221.1Sskrll#define MUXF_UA3_TX 102 1231.1Sskrll#define MUXF_UA3_RX 103 1241.1Sskrll#define MUXF_UA3_CTS 104 1251.1Sskrll#define MUXF_UA3_RTS 105 1261.1Sskrll#define MUXF_UA4_TX 106 1271.1Sskrll#define MUXF_UA4_RX 107 1281.1Sskrll#define MUXF_UA4_CTS 108 1291.1Sskrll#define MUXF_UA4_RTS 109 1301.1Sskrll#define MUXF_TIMER0_INT 110 1311.1Sskrll#define MUXF_TIMER1_INT 111 1321.1Sskrll#define MUXF_TIMER2_INT 112 1331.1Sskrll#define MUXF_TIMER3_INT 113 1341.1Sskrll#define MUXF_GPIO_INT0 114 1351.1Sskrll#define MUXF_GPIO_INT1 115 1361.1Sskrll#define MUXF_GPIO_INT2 116 1371.1Sskrll#define MUXF_GPIO_INT3 117 1381.1Sskrll#define MUXF_GPIO_INT4 118 1391.1Sskrll#define MUXF_GPIO_INT5 119 1401.1Sskrll#define MUXF_GPIO_INT6 120 1411.1Sskrll#define MUXF_GPIO_INT7 121 1421.1Sskrll 1431.1Sskrll/* 1441.1Sskrll * Please don't change the order of the following defines. 1451.1Sskrll * They are based on order of items in array 'sppctl_list_funcs' 1461.1Sskrll * in Sunplus pinctrl driver. 1471.1Sskrll */ 1481.1Sskrll#define GROP_SPI_FLASH 122 1491.1Sskrll#define GROP_SPI_FLASH_4BIT 123 1501.1Sskrll#define GROP_SPI_NAND 124 1511.1Sskrll#define GROP_CARD0_EMMC 125 1521.1Sskrll#define GROP_SD_CARD 126 1531.1Sskrll#define GROP_UA0 127 1541.1Sskrll#define GROP_ACHIP_DEBUG 128 1551.1Sskrll#define GROP_ACHIP_UA2AXI 129 1561.1Sskrll#define GROP_FPGA_IFX 130 1571.1Sskrll#define GROP_HDMI_TX 131 1581.1Sskrll#define GROP_AUD_EXT_ADC_IFX0 132 1591.1Sskrll#define GROP_AUD_EXT_DAC_IFX0 133 1601.1Sskrll#define GROP_SPDIF_RX 134 1611.1Sskrll#define GROP_SPDIF_TX 135 1621.1Sskrll#define GROP_TDMTX_IFX0 136 1631.1Sskrll#define GROP_TDMRX_IFX0 137 1641.1Sskrll#define GROP_PDMRX_IFX0 138 1651.1Sskrll#define GROP_PCM_IEC_TX 139 1661.1Sskrll#define GROP_LCDIF 140 1671.1Sskrll#define GROP_DVD_DSP_DEBUG 141 1681.1Sskrll#define GROP_I2C_DEBUG 142 1691.1Sskrll#define GROP_I2C_SLAVE 143 1701.1Sskrll#define GROP_WAKEUP 144 1711.1Sskrll#define GROP_UART2AXI 145 1721.1Sskrll#define GROP_USB0_I2C 146 1731.1Sskrll#define GROP_USB1_I2C 147 1741.1Sskrll#define GROP_USB0_OTG 148 1751.1Sskrll#define GROP_USB1_OTG 149 1761.1Sskrll#define GROP_UPHY0_DEBUG 150 1771.1Sskrll#define GROP_UPHY1_DEBUG 151 1781.1Sskrll#define GROP_UPHY0_EXT 152 1791.1Sskrll#define GROP_PROBE_PORT 153 1801.1Sskrll 1811.1Sskrll#endif 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