1 1.1 jmcneill /* $NetBSD: r8a7795-sysc.h,v 1.1.1.3 2020/01/03 14:33:03 skrll Exp $ */ 2 1.1 jmcneill 3 1.1.1.3 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (C) 2016 Glider bvba 6 1.1 jmcneill */ 7 1.1 jmcneill #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ 8 1.1 jmcneill #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ 9 1.1 jmcneill 10 1.1 jmcneill /* 11 1.1 jmcneill * These power domain indices match the numbers of the interrupt bits 12 1.1 jmcneill * representing the power areas in the various Interrupt Registers 13 1.1 jmcneill * (e.g. SYSCISR, Interrupt Status Register) 14 1.1 jmcneill */ 15 1.1 jmcneill 16 1.1 jmcneill #define R8A7795_PD_CA57_CPU0 0 17 1.1 jmcneill #define R8A7795_PD_CA57_CPU1 1 18 1.1 jmcneill #define R8A7795_PD_CA57_CPU2 2 19 1.1 jmcneill #define R8A7795_PD_CA57_CPU3 3 20 1.1 jmcneill #define R8A7795_PD_CA53_CPU0 5 21 1.1 jmcneill #define R8A7795_PD_CA53_CPU1 6 22 1.1 jmcneill #define R8A7795_PD_CA53_CPU2 7 23 1.1 jmcneill #define R8A7795_PD_CA53_CPU3 8 24 1.1 jmcneill #define R8A7795_PD_A3VP 9 25 1.1 jmcneill #define R8A7795_PD_CA57_SCU 12 26 1.1 jmcneill #define R8A7795_PD_CR7 13 27 1.1 jmcneill #define R8A7795_PD_A3VC 14 28 1.1 jmcneill #define R8A7795_PD_3DG_A 17 29 1.1 jmcneill #define R8A7795_PD_3DG_B 18 30 1.1 jmcneill #define R8A7795_PD_3DG_C 19 31 1.1 jmcneill #define R8A7795_PD_3DG_D 20 32 1.1 jmcneill #define R8A7795_PD_CA53_SCU 21 33 1.1 jmcneill #define R8A7795_PD_3DG_E 22 34 1.1 jmcneill #define R8A7795_PD_A3IR 24 35 1.1.1.2 jmcneill #define R8A7795_PD_A2VC0 25 /* ES1.x only */ 36 1.1 jmcneill #define R8A7795_PD_A2VC1 26 37 1.1 jmcneill 38 1.1 jmcneill /* Always-on power area */ 39 1.1 jmcneill #define R8A7795_PD_ALWAYS_ON 32 40 1.1 jmcneill 41 1.1 jmcneill #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ 42
Indexes created Tue Sep 30 17:09:57 GMT 2025