1 1.1 jmcneill /* $NetBSD: mt8192-resets.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2020 MediaTek Inc. 6 1.1 jmcneill * Author: Yong Liang <yong.liang (at) mediatek.com> 7 1.1 jmcneill */ 8 1.1 jmcneill 9 1.1 jmcneill #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 10 1.1 jmcneill #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 11 1.1 jmcneill 12 1.1 jmcneill #define MT8192_TOPRGU_MM_SW_RST 1 13 1.1 jmcneill #define MT8192_TOPRGU_MFG_SW_RST 2 14 1.1 jmcneill #define MT8192_TOPRGU_VENC_SW_RST 3 15 1.1 jmcneill #define MT8192_TOPRGU_VDEC_SW_RST 4 16 1.1 jmcneill #define MT8192_TOPRGU_IMG_SW_RST 5 17 1.1 jmcneill #define MT8192_TOPRGU_MD_SW_RST 7 18 1.1 jmcneill #define MT8192_TOPRGU_CONN_SW_RST 9 19 1.1 jmcneill #define MT8192_TOPRGU_CONN_MCU_SW_RST 12 20 1.1 jmcneill #define MT8192_TOPRGU_IPU0_SW_RST 14 21 1.1 jmcneill #define MT8192_TOPRGU_IPU1_SW_RST 15 22 1.1 jmcneill #define MT8192_TOPRGU_AUDIO_SW_RST 17 23 1.1 jmcneill #define MT8192_TOPRGU_CAMSYS_SW_RST 18 24 1.1 jmcneill #define MT8192_TOPRGU_MJC_SW_RST 19 25 1.1 jmcneill #define MT8192_TOPRGU_C2K_S2_SW_RST 20 26 1.1 jmcneill #define MT8192_TOPRGU_C2K_SW_RST 21 27 1.1 jmcneill #define MT8192_TOPRGU_PERI_SW_RST 22 28 1.1 jmcneill #define MT8192_TOPRGU_PERI_AO_SW_RST 23 29 1.1 jmcneill 30 1.1 jmcneill #define MT8192_TOPRGU_SW_RST_NUM 23 31 1.1 jmcneill 32 1.1 jmcneill #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ 33
Indexes created Tue Oct 07 07:09:48 GMT 2025