11.1Sjmcneill/* $NetBSD: altr,rst-mgr-s10.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-only */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (C) 2016 Intel Corporation. All rights reserved 61.1Sjmcneill * Copyright (C) 2016 Altera Corporation. All rights reserved 71.1Sjmcneill * 81.1Sjmcneill * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" 91.1Sjmcneill */ 101.1Sjmcneill 111.1Sjmcneill#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 121.1Sjmcneill#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 131.1Sjmcneill 141.1Sjmcneill/* MPUMODRST */ 151.1Sjmcneill#define CPU0_RESET 0 161.1Sjmcneill#define CPU1_RESET 1 171.1Sjmcneill#define CPU2_RESET 2 181.1Sjmcneill#define CPU3_RESET 3 191.1Sjmcneill 201.1Sjmcneill/* PER0MODRST */ 211.1Sjmcneill#define EMAC0_RESET 32 221.1Sjmcneill#define EMAC1_RESET 33 231.1Sjmcneill#define EMAC2_RESET 34 241.1Sjmcneill#define USB0_RESET 35 251.1Sjmcneill#define USB1_RESET 36 261.1Sjmcneill#define NAND_RESET 37 271.1Sjmcneill/* 38 is empty */ 281.1Sjmcneill#define SDMMC_RESET 39 291.1Sjmcneill#define EMAC0_OCP_RESET 40 301.1Sjmcneill#define EMAC1_OCP_RESET 41 311.1Sjmcneill#define EMAC2_OCP_RESET 42 321.1Sjmcneill#define USB0_OCP_RESET 43 331.1Sjmcneill#define USB1_OCP_RESET 44 341.1Sjmcneill#define NAND_OCP_RESET 45 351.1Sjmcneill/* 46 is empty */ 361.1Sjmcneill#define SDMMC_OCP_RESET 47 371.1Sjmcneill#define DMA_RESET 48 381.1Sjmcneill#define SPIM0_RESET 49 391.1Sjmcneill#define SPIM1_RESET 50 401.1Sjmcneill#define SPIS0_RESET 51 411.1Sjmcneill#define SPIS1_RESET 52 421.1Sjmcneill#define DMA_OCP_RESET 53 431.1Sjmcneill#define EMAC_PTP_RESET 54 441.1Sjmcneill/* 55 is empty*/ 451.1Sjmcneill#define DMAIF0_RESET 56 461.1Sjmcneill#define DMAIF1_RESET 57 471.1Sjmcneill#define DMAIF2_RESET 58 481.1Sjmcneill#define DMAIF3_RESET 59 491.1Sjmcneill#define DMAIF4_RESET 60 501.1Sjmcneill#define DMAIF5_RESET 61 511.1Sjmcneill#define DMAIF6_RESET 62 521.1Sjmcneill#define DMAIF7_RESET 63 531.1Sjmcneill 541.1Sjmcneill/* PER1MODRST */ 551.1Sjmcneill#define WATCHDOG0_RESET 64 561.1Sjmcneill#define WATCHDOG1_RESET 65 571.1Sjmcneill#define WATCHDOG2_RESET 66 581.1Sjmcneill#define WATCHDOG3_RESET 67 591.1Sjmcneill#define L4SYSTIMER0_RESET 68 601.1Sjmcneill#define L4SYSTIMER1_RESET 69 611.1Sjmcneill#define SPTIMER0_RESET 70 621.1Sjmcneill#define SPTIMER1_RESET 71 631.1Sjmcneill#define I2C0_RESET 72 641.1Sjmcneill#define I2C1_RESET 73 651.1Sjmcneill#define I2C2_RESET 74 661.1Sjmcneill#define I2C3_RESET 75 671.1Sjmcneill#define I2C4_RESET 76 681.1Sjmcneill/* 77-79 is empty */ 691.1Sjmcneill#define UART0_RESET 80 701.1Sjmcneill#define UART1_RESET 81 711.1Sjmcneill/* 82-87 is empty */ 721.1Sjmcneill#define GPIO0_RESET 88 731.1Sjmcneill#define GPIO1_RESET 89 741.1Sjmcneill 751.1Sjmcneill/* BRGMODRST */ 761.1Sjmcneill#define SOC2FPGA_RESET 96 771.1Sjmcneill#define LWHPS2FPGA_RESET 97 781.1Sjmcneill#define FPGA2SOC_RESET 98 791.1Sjmcneill#define F2SSDRAM0_RESET 99 801.1Sjmcneill#define F2SSDRAM1_RESET 100 811.1Sjmcneill#define F2SSDRAM2_RESET 101 821.1Sjmcneill#define DDRSCH_RESET 102 831.1Sjmcneill 841.1Sjmcneill/* COLDMODRST */ 851.1Sjmcneill#define CPUPO0_RESET 160 861.1Sjmcneill#define CPUPO1_RESET 161 871.1Sjmcneill#define CPUPO2_RESET 162 881.1Sjmcneill#define CPUPO3_RESET 163 891.1Sjmcneill/* 164-167 is empty */ 901.1Sjmcneill#define L2_RESET 168 911.1Sjmcneill 921.1Sjmcneill/* DBGMODRST */ 931.1Sjmcneill#define DBG_RESET 224 941.1Sjmcneill#define CSDAP_RESET 225 951.1Sjmcneill 961.1Sjmcneill/* TAPMODRST */ 971.1Sjmcneill#define TAP_RESET 256 981.1Sjmcneill 991.1Sjmcneill#endif 100