Home | History | Annotate | Line # | Download | only in reset
altr,rst-mgr-s10.h revision 1.1 
      1 /*	$NetBSD: altr,rst-mgr-s10.h,v 1.1 2017/10/28 10:30:32 jmcneill Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 2016 Intel Corporation. All rights reserved
      5  * Copyright (C) 2016 Altera Corporation. All rights reserved
      6  *
      7  * This program is free software; you can redistribute it and/or modify
      8  * it under the terms and conditions of the GNU General Public License,
      9  * version 2, as published by the Free Software Foundation.
     10  *
     11  * This program is distributed in the hope it will be useful, but WITHOUT
     12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     14  * more details.
     15  *
     16  * You should have received a copy of the GNU General Public License along with
     17  * this program.  If not, see <http://www.gnu.org/licenses/>.
     18  *
     19  * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
     20  */
     21 
     22 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
     23 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
     24 
     25 /* MPUMODRST */
     26 #define CPU0_RESET		0
     27 #define CPU1_RESET		1
     28 #define CPU2_RESET		2
     29 #define CPU3_RESET		3
     30 
     31 /* PER0MODRST */
     32 #define EMAC0_RESET		32
     33 #define EMAC1_RESET		33
     34 #define EMAC2_RESET		34
     35 #define USB0_RESET		35
     36 #define USB1_RESET		36
     37 #define NAND_RESET		37
     38 /* 38 is empty */
     39 #define SDMMC_RESET		39
     40 #define EMAC0_OCP_RESET		40
     41 #define EMAC1_OCP_RESET		41
     42 #define EMAC2_OCP_RESET		42
     43 #define USB0_OCP_RESET		43
     44 #define USB1_OCP_RESET		44
     45 #define NAND_OCP_RESET		45
     46 /* 46 is empty */
     47 #define SDMMC_OCP_RESET		47
     48 #define DMA_RESET		48
     49 #define SPIM0_RESET		49
     50 #define SPIM1_RESET		50
     51 #define SPIS0_RESET		51
     52 #define SPIS1_RESET		52
     53 #define DMA_OCP_RESET		53
     54 #define EMAC_PTP_RESET		54
     55 /* 55 is empty*/
     56 #define DMAIF0_RESET		56
     57 #define DMAIF1_RESET		57
     58 #define DMAIF2_RESET		58
     59 #define DMAIF3_RESET		59
     60 #define DMAIF4_RESET		60
     61 #define DMAIF5_RESET		61
     62 #define DMAIF6_RESET		62
     63 #define DMAIF7_RESET		63
     64 
     65 /* PER1MODRST */
     66 #define WATCHDOG0_RESET		64
     67 #define WATCHDOG1_RESET		65
     68 #define WATCHDOG2_RESET		66
     69 #define WATCHDOG3_RESET		67
     70 #define L4SYSTIMER0_RESET	68
     71 #define L4SYSTIMER1_RESET	69
     72 #define SPTIMER0_RESET		70
     73 #define SPTIMER1_RESET		71
     74 #define I2C0_RESET		72
     75 #define I2C1_RESET		73
     76 #define I2C2_RESET		74
     77 #define I2C3_RESET		75
     78 #define I2C4_RESET		76
     79 /* 77-79 is empty */
     80 #define UART0_RESET		80
     81 #define UART1_RESET		81
     82 /* 82-87 is empty */
     83 #define GPIO0_RESET		88
     84 #define GPIO1_RESET		89
     85 
     86 /* BRGMODRST */
     87 #define SOC2FPGA_RESET		96
     88 #define LWHPS2FPGA_RESET	97
     89 #define FPGA2SOC_RESET		98
     90 #define F2SSDRAM0_RESET		99
     91 #define F2SSDRAM1_RESET		100
     92 #define F2SSDRAM2_RESET		101
     93 #define DDRSCH_RESET		102
     94 
     95 /* COLDMODRST */
     96 #define CPUPO0_RESET		160
     97 #define CPUPO1_RESET		161
     98 #define CPUPO2_RESET		162
     99 #define CPUPO3_RESET		163
    100 /* 164-167 is empty */
    101 #define L2_RESET		168
    102 
    103 /* DBGMODRST */
    104 #define DBG_RESET		224
    105 #define CSDAP_RESET		225
    106 
    107 /* TAPMODRST */
    108 #define TAP_RESET		256
    109 
    110 #endif
    111