amlogic,meson-axg-reset.h revision 1.1.1.1 
1/*	$NetBSD: amlogic,meson-axg-reset.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $	*/
2
3/*
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Yixun Lan <yixun.lan@amlogic.com>
10 *
11 * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
12 */
13
14#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
15#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
16
17/*	RESET0					*/
18#define RESET_HIU			0
19#define RESET_PCIE_A			1
20#define RESET_PCIE_B			2
21#define RESET_DDR_TOP			3
22/*					4	*/
23#define RESET_VIU			5
24#define RESET_PCIE_PHY			6
25#define RESET_PCIE_APB			7
26/*					8	*/
27/*					9	*/
28#define RESET_VENC			10
29#define RESET_ASSIST			11
30/*					12	*/
31#define RESET_VCBUS			13
32/*					14	*/
33/*					15	*/
34#define RESET_GIC			16
35#define RESET_CAPB3_DECODE		17
36/*					18-21	*/
37#define RESET_SYS_CPU_CAPB3		22
38#define RESET_CBUS_CAPB3		23
39#define RESET_AHB_CNTL			24
40#define RESET_AHB_DATA			25
41#define RESET_VCBUS_CLK81		26
42#define RESET_MMC			27
43/*					28-31	*/
44/*	RESET1					*/
45/*					32	*/
46/*					33	*/
47#define RESET_USB_OTG			34
48#define RESET_DDR			35
49#define RESET_AO_RESET			36
50/*					37	*/
51#define RESET_AHB_SRAM			38
52/*					39	*/
53/*					40	*/
54#define RESET_DMA			41
55#define RESET_ISA			42
56#define RESET_ETHERNET			43
57/*					44	*/
58#define RESET_SD_EMMC_B			45
59#define RESET_SD_EMMC_C			46
60#define RESET_ROM_BOOT			47
61#define RESET_SYS_CPU_0			48
62#define RESET_SYS_CPU_1			49
63#define RESET_SYS_CPU_2			50
64#define RESET_SYS_CPU_3			51
65#define RESET_SYS_CPU_CORE_0		52
66#define RESET_SYS_CPU_CORE_1		53
67#define RESET_SYS_CPU_CORE_2		54
68#define RESET_SYS_CPU_CORE_3		55
69#define RESET_SYS_PLL_DIV		56
70#define RESET_SYS_CPU_AXI		57
71#define RESET_SYS_CPU_L2		58
72#define RESET_SYS_CPU_P			59
73#define RESET_SYS_CPU_MBIST		60
74/*					61-63	*/
75/*	RESET2					*/
76/*					64	*/
77/*					65	*/
78#define RESET_AUDIO			66
79/*					67	*/
80#define RESET_MIPI_HOST			68
81#define RESET_AUDIO_LOCKER		69
82#define RESET_GE2D			70
83/*					71-76	*/
84#define RESET_AO_CPU_RESET		77
85/*					78-95	*/
86/*	RESET3					*/
87#define RESET_RING_OSCILLATOR		96
88/*					97-127	*/
89/*	RESET4					*/
90/*					128	*/
91/*					129	*/
92#define RESET_MIPI_PHY			130
93/*					131-140	*/
94#define RESET_VENCL			141
95#define RESET_I2C_MASTER_2		142
96#define RESET_I2C_MASTER_1		143
97/*					144-159	*/
98/*	RESET5					*/
99/*					160-191	*/
100/*	RESET6					*/
101#define RESET_PERIPHS_GENERAL		192
102#define RESET_PERIPHS_SPICC		193
103/*					194	*/
104/*					195	*/
105#define RESET_PERIPHS_I2C_MASTER_0	196
106/*					197-200	*/
107#define RESET_PERIPHS_UART_0		201
108#define RESET_PERIPHS_UART_1		202
109/*					203-204	*/
110#define RESET_PERIPHS_SPI_0		205
111#define RESET_PERIPHS_I2C_MASTER_3	206
112/*					207-223	*/
113/*	RESET7					*/
114#define RESET_USB_DDR_0			224
115#define RESET_USB_DDR_1			225
116#define RESET_USB_DDR_2			226
117#define RESET_USB_DDR_3			227
118/*					228	*/
119#define RESET_DEVICE_MMC_ARB		229
120/*					230	*/
121#define RESET_VID_LOCK			231
122#define RESET_A9_DMC_PIPEL		232
123#define RESET_DMC_VPU_PIPEL		233
124/*					234-255	*/
125
126#endif
127