amlogic,meson-axg-reset.h revision 1.1.1.2 
1/*	$NetBSD: amlogic,meson-axg-reset.h,v 1.1.1.2 2019/05/25 11:29:13 jmcneill Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
4/*
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Yixun Lan <yixun.lan@amlogic.com>
10 *
11 */
12
13#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
14#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
15
16/*	RESET0					*/
17#define RESET_HIU			0
18#define RESET_PCIE_A			1
19#define RESET_PCIE_B			2
20#define RESET_DDR_TOP			3
21/*					4	*/
22#define RESET_VIU			5
23#define RESET_PCIE_PHY			6
24#define RESET_PCIE_APB			7
25/*					8	*/
26/*					9	*/
27#define RESET_VENC			10
28#define RESET_ASSIST			11
29/*					12	*/
30#define RESET_VCBUS			13
31/*					14	*/
32/*					15	*/
33#define RESET_GIC			16
34#define RESET_CAPB3_DECODE		17
35/*					18-21	*/
36#define RESET_SYS_CPU_CAPB3		22
37#define RESET_CBUS_CAPB3		23
38#define RESET_AHB_CNTL			24
39#define RESET_AHB_DATA			25
40#define RESET_VCBUS_CLK81		26
41#define RESET_MMC			27
42/*					28-31	*/
43/*	RESET1					*/
44/*					32	*/
45/*					33	*/
46#define RESET_USB_OTG			34
47#define RESET_DDR			35
48#define RESET_AO_RESET			36
49/*					37	*/
50#define RESET_AHB_SRAM			38
51/*					39	*/
52/*					40	*/
53#define RESET_DMA			41
54#define RESET_ISA			42
55#define RESET_ETHERNET			43
56/*					44	*/
57#define RESET_SD_EMMC_B			45
58#define RESET_SD_EMMC_C			46
59#define RESET_ROM_BOOT			47
60#define RESET_SYS_CPU_0			48
61#define RESET_SYS_CPU_1			49
62#define RESET_SYS_CPU_2			50
63#define RESET_SYS_CPU_3			51
64#define RESET_SYS_CPU_CORE_0		52
65#define RESET_SYS_CPU_CORE_1		53
66#define RESET_SYS_CPU_CORE_2		54
67#define RESET_SYS_CPU_CORE_3		55
68#define RESET_SYS_PLL_DIV		56
69#define RESET_SYS_CPU_AXI		57
70#define RESET_SYS_CPU_L2		58
71#define RESET_SYS_CPU_P			59
72#define RESET_SYS_CPU_MBIST		60
73/*					61-63	*/
74/*	RESET2					*/
75/*					64	*/
76/*					65	*/
77#define RESET_AUDIO			66
78/*					67	*/
79#define RESET_MIPI_HOST			68
80#define RESET_AUDIO_LOCKER		69
81#define RESET_GE2D			70
82/*					71-76	*/
83#define RESET_AO_CPU_RESET		77
84/*					78-95	*/
85/*	RESET3					*/
86#define RESET_RING_OSCILLATOR		96
87/*					97-127	*/
88/*	RESET4					*/
89/*					128	*/
90/*					129	*/
91#define RESET_MIPI_PHY			130
92/*					131-140	*/
93#define RESET_VENCL			141
94#define RESET_I2C_MASTER_2		142
95#define RESET_I2C_MASTER_1		143
96/*					144-159	*/
97/*	RESET5					*/
98/*					160-191	*/
99/*	RESET6					*/
100#define RESET_PERIPHS_GENERAL		192
101#define RESET_PERIPHS_SPICC		193
102/*					194	*/
103/*					195	*/
104#define RESET_PERIPHS_I2C_MASTER_0	196
105/*					197-200	*/
106#define RESET_PERIPHS_UART_0		201
107#define RESET_PERIPHS_UART_1		202
108/*					203-204	*/
109#define RESET_PERIPHS_SPI_0		205
110#define RESET_PERIPHS_I2C_MASTER_3	206
111/*					207-223	*/
112/*	RESET7					*/
113#define RESET_USB_DDR_0			224
114#define RESET_USB_DDR_1			225
115#define RESET_USB_DDR_2			226
116#define RESET_USB_DDR_3			227
117/*					228	*/
118#define RESET_DEVICE_MMC_ARB		229
119/*					230	*/
120#define RESET_VID_LOCK			231
121#define RESET_A9_DMC_PIPEL		232
122#define RESET_DMC_VPU_PIPEL		233
123/*					234-255	*/
124
125#endif
126