amlogic,meson-s4-reset.h revision 1.1.1.1 
1/*	$NetBSD: amlogic,meson-s4-reset.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
4/*
5 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
6 * Author: Zelong Dong <zelong.dong@amlogic.com>
7 *
8 */
9
10#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
11#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
12
13/*	RESET0					*/
14#define RESET_USB_DDR0			0
15#define RESET_USB_DDR1			1
16#define RESET_USB_DDR2			2
17#define RESET_USB_DDR3			3
18#define RESET_USBCTRL			4
19/*					5-7	*/
20#define RESET_USBPHY20			8
21#define RESET_USBPHY21			9
22/*					10-15	*/
23#define RESET_HDMITX_APB		16
24#define RESET_BRG_VCBUS_DEC		17
25#define RESET_VCBUS			18
26#define RESET_VID_PLL_DIV		19
27#define RESET_VDI6			20
28#define RESET_GE2D			21
29#define RESET_HDMITXPHY			22
30#define RESET_VID_LOCK			23
31#define RESET_VENCL			24
32#define RESET_VDAC			25
33#define RESET_VENCP			26
34#define RESET_VENCI			27
35#define RESET_RDMA			28
36#define RESET_HDMI_TX			29
37#define RESET_VIU			30
38#define RESET_VENC			31
39
40/*	RESET1					*/
41#define RESET_AUDIO			32
42#define RESET_MALI_APB			33
43#define RESET_MALI			34
44#define RESET_DDR_APB			35
45#define RESET_DDR			36
46#define RESET_DOS_APB			37
47#define RESET_DOS			38
48/*					39-47	*/
49#define RESET_ETH			48
50/*					49-51	*/
51#define RESET_DEMOD			52
52/*					53-63	*/
53
54/*	RESET2					*/
55#define RESET_ABUS_ARB			64
56#define RESET_IR_CTRL			65
57#define RESET_TEMPSENSOR_DDR		66
58#define RESET_TEMPSENSOR_PLL		67
59/*					68-71	*/
60#define RESET_SMART_CARD		72
61#define RESET_SPICC0			73
62/*					74	*/
63#define RESET_RSA			75
64/*					76-79	*/
65#define RESET_MSR_CLK			80
66#define RESET_SPIFC			81
67#define RESET_SARADC			82
68/*					83-87	*/
69#define RESET_ACODEC			88
70#define RESET_CEC			89
71#define RESET_AFIFO			90
72#define RESET_WATCHDOG			91
73/*					92-95	*/
74
75/*	RESET3					*/
76/*					96-127	*/
77
78/*	RESET4					*/
79/*					128-131	*/
80#define RESET_PWM_AB			132
81#define RESET_PWM_CD			133
82#define RESET_PWM_EF			134
83#define RESET_PWM_GH			135
84#define RESET_PWM_IJ			136
85/*					137	*/
86#define RESET_UART_A			138
87#define RESET_UART_B			139
88#define RESET_UART_C			140
89#define RESET_UART_D			141
90#define RESET_UART_E			142
91/*					143	*/
92#define RESET_I2C_S_A			144
93#define RESET_I2C_M_A			145
94#define RESET_I2C_M_B			146
95#define RESET_I2C_M_C			147
96#define RESET_I2C_M_D			148
97#define RESET_I2C_M_E			149
98/*					150-151	*/
99#define RESET_SD_EMMC_A			152
100#define RESET_SD_EMMC_B			153
101#define RESET_NAND_EMMC			154
102/*					155-159	*/
103
104/* RESET5 */
105#define RESET_BRG_VDEC_PIPL0		160
106#define RESET_BRG_HEVCF_PIPL0		161
107/*					162	*/
108#define RESET_BRG_HCODEC_PIPL0		163
109#define RESET_BRG_GE2D_PIPL0		164
110#define RESET_BRG_VPU_PIPL0		165
111#define RESET_BRG_CPU_PIPL0		166
112#define RESET_BRG_MALI_PIPL0		167
113/*					168	*/
114#define RESET_BRG_MALI_PIPL1		169
115/*					170-171	*/
116#define RESET_BRG_HEVCF_PIPL1		172
117#define RESET_BRG_HEVCB_PIPL1		173
118/*					174-183	*/
119#define RESET_RAMA			184
120/*					185-186	*/
121#define RESET_BRG_NIC_VAPB		187
122#define RESET_BRG_NIC_DSU		188
123#define RESET_BRG_NIC_SYSCLK		189
124#define RESET_BRG_NIC_MAIN		190
125#define RESET_BRG_NIC_ALL		191
126
127#endif
128