11.1Sjmcneill/* $NetBSD: amlogic,meson8b-clkc-reset.h,v 1.1.1.1 2017/10/28 10:30:32 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* 41.1Sjmcneill * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. 51.1Sjmcneill * 61.1Sjmcneill * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 71.1Sjmcneill */ 81.1Sjmcneill 91.1Sjmcneill#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H 101.1Sjmcneill#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H 111.1Sjmcneill 121.1Sjmcneill#define CLKC_RESET_L2_CACHE_SOFT_RESET 0 131.1Sjmcneill#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1 141.1Sjmcneill#define CLKC_RESET_SCU_SOFT_RESET 2 151.1Sjmcneill#define CLKC_RESET_CPU0_SOFT_RESET 3 161.1Sjmcneill#define CLKC_RESET_CPU1_SOFT_RESET 4 171.1Sjmcneill#define CLKC_RESET_CPU2_SOFT_RESET 5 181.1Sjmcneill#define CLKC_RESET_CPU3_SOFT_RESET 6 191.1Sjmcneill#define CLKC_RESET_A5_GLOBAL_RESET 7 201.1Sjmcneill#define CLKC_RESET_A5_AXI_SOFT_RESET 8 211.1Sjmcneill#define CLKC_RESET_A5_ABP_SOFT_RESET 9 221.1Sjmcneill#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10 231.1Sjmcneill#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11 241.1Sjmcneill#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12 251.1Sjmcneill#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13 261.1Sjmcneill#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14 271.1Sjmcneill#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15 281.1Sjmcneill 291.1Sjmcneill#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */ 30