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      1  1.1  jmcneill /*	$NetBSD: amlogic,meson8b-clkc-reset.h,v 1.1.1.1 2017/10/28 10:30:32 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /*
      4  1.1  jmcneill  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl (at) googlemail.com>.
      5  1.1  jmcneill  *
      6  1.1  jmcneill  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      7  1.1  jmcneill  */
      8  1.1  jmcneill 
      9  1.1  jmcneill #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
     10  1.1  jmcneill #define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
     11  1.1  jmcneill 
     12  1.1  jmcneill #define CLKC_RESET_L2_CACHE_SOFT_RESET				0
     13  1.1  jmcneill #define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
     14  1.1  jmcneill #define CLKC_RESET_SCU_SOFT_RESET				2
     15  1.1  jmcneill #define CLKC_RESET_CPU0_SOFT_RESET				3
     16  1.1  jmcneill #define CLKC_RESET_CPU1_SOFT_RESET				4
     17  1.1  jmcneill #define CLKC_RESET_CPU2_SOFT_RESET				5
     18  1.1  jmcneill #define CLKC_RESET_CPU3_SOFT_RESET				6
     19  1.1  jmcneill #define CLKC_RESET_A5_GLOBAL_RESET				7
     20  1.1  jmcneill #define CLKC_RESET_A5_AXI_SOFT_RESET				8
     21  1.1  jmcneill #define CLKC_RESET_A5_ABP_SOFT_RESET				9
     22  1.1  jmcneill #define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET		10
     23  1.1  jmcneill #define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET			11
     24  1.1  jmcneill #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST		12
     25  1.1  jmcneill #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE		13
     26  1.1  jmcneill #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST		14
     27  1.1  jmcneill #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE			15
     28  1.1  jmcneill 
     29  1.1  jmcneill #endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
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