11.1Sskrll/* $NetBSD: bitmain,bm1880-reset.h,v 1.1.1.1 2020/01/03 14:33:06 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0+ */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2018 Bitmain Ltd. 61.1Sskrll * Copyright (c) 2019 Linaro Ltd. 71.1Sskrll */ 81.1Sskrll 91.1Sskrll#ifndef _DT_BINDINGS_BM1880_RESET_H 101.1Sskrll#define _DT_BINDINGS_BM1880_RESET_H 111.1Sskrll 121.1Sskrll#define BM1880_RST_MAIN_AP 0 131.1Sskrll#define BM1880_RST_SECOND_AP 1 141.1Sskrll#define BM1880_RST_DDR 2 151.1Sskrll#define BM1880_RST_VIDEO 3 161.1Sskrll#define BM1880_RST_JPEG 4 171.1Sskrll#define BM1880_RST_VPP 5 181.1Sskrll#define BM1880_RST_GDMA 6 191.1Sskrll#define BM1880_RST_AXI_SRAM 7 201.1Sskrll#define BM1880_RST_TPU 8 211.1Sskrll#define BM1880_RST_USB 9 221.1Sskrll#define BM1880_RST_ETH0 10 231.1Sskrll#define BM1880_RST_ETH1 11 241.1Sskrll#define BM1880_RST_NAND 12 251.1Sskrll#define BM1880_RST_EMMC 13 261.1Sskrll#define BM1880_RST_SD 14 271.1Sskrll#define BM1880_RST_SDMA 15 281.1Sskrll#define BM1880_RST_I2S0 16 291.1Sskrll#define BM1880_RST_I2S1 17 301.1Sskrll#define BM1880_RST_UART0_1_CLK 18 311.1Sskrll#define BM1880_RST_UART0_1_ACLK 19 321.1Sskrll#define BM1880_RST_UART2_3_CLK 20 331.1Sskrll#define BM1880_RST_UART2_3_ACLK 21 341.1Sskrll#define BM1880_RST_MINER 22 351.1Sskrll#define BM1880_RST_I2C0 23 361.1Sskrll#define BM1880_RST_I2C1 24 371.1Sskrll#define BM1880_RST_I2C2 25 381.1Sskrll#define BM1880_RST_I2C3 26 391.1Sskrll#define BM1880_RST_I2C4 27 401.1Sskrll#define BM1880_RST_PWM0 28 411.1Sskrll#define BM1880_RST_PWM1 29 421.1Sskrll#define BM1880_RST_PWM2 30 431.1Sskrll#define BM1880_RST_PWM3 31 441.1Sskrll#define BM1880_RST_SPI 32 451.1Sskrll#define BM1880_RST_GPIO0 33 461.1Sskrll#define BM1880_RST_GPIO1 34 471.1Sskrll#define BM1880_RST_GPIO2 35 481.1Sskrll#define BM1880_RST_EFUSE 36 491.1Sskrll#define BM1880_RST_WDT 37 501.1Sskrll#define BM1880_RST_AHB_ROM 38 511.1Sskrll#define BM1880_RST_SPIC 39 521.1Sskrll 531.1Sskrll#endif /* _DT_BINDINGS_BM1880_RESET_H */ 54