11.1Sjmcneill/* $NetBSD: hisi,hi6220-resets.h,v 1.1.1.3 2020/01/03 14:33:06 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sjmcneill/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sjmcneill/** 51.1Sjmcneill * This header provides index for the reset controller 61.1Sjmcneill * based on hi6220 SoC. 71.1Sjmcneill */ 81.1Sjmcneill#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 91.1Sjmcneill#define _DT_BINDINGS_RESET_CONTROLLER_HI6220 101.1Sjmcneill 111.1Sjmcneill#define PERIPH_RSTDIS0_MMC0 0x000 121.1Sjmcneill#define PERIPH_RSTDIS0_MMC1 0x001 131.1Sjmcneill#define PERIPH_RSTDIS0_MMC2 0x002 141.1Sjmcneill#define PERIPH_RSTDIS0_NANDC 0x003 151.1Sjmcneill#define PERIPH_RSTDIS0_USBOTG_BUS 0x004 161.1Sjmcneill#define PERIPH_RSTDIS0_POR_PICOPHY 0x005 171.1Sjmcneill#define PERIPH_RSTDIS0_USBOTG 0x006 181.1Sjmcneill#define PERIPH_RSTDIS0_USBOTG_32K 0x007 191.1Sjmcneill#define PERIPH_RSTDIS1_HIFI 0x100 201.1Sjmcneill#define PERIPH_RSTDIS1_DIGACODEC 0x105 211.1Sjmcneill#define PERIPH_RSTEN2_IPF 0x200 221.1Sjmcneill#define PERIPH_RSTEN2_SOCP 0x201 231.1Sjmcneill#define PERIPH_RSTEN2_DMAC 0x202 241.1Sjmcneill#define PERIPH_RSTEN2_SECENG 0x203 251.1Sjmcneill#define PERIPH_RSTEN2_ABB 0x204 261.1Sjmcneill#define PERIPH_RSTEN2_HPM0 0x205 271.1Sjmcneill#define PERIPH_RSTEN2_HPM1 0x206 281.1Sjmcneill#define PERIPH_RSTEN2_HPM2 0x207 291.1Sjmcneill#define PERIPH_RSTEN2_HPM3 0x208 301.1Sjmcneill#define PERIPH_RSTEN3_CSSYS 0x300 311.1Sjmcneill#define PERIPH_RSTEN3_I2C0 0x301 321.1Sjmcneill#define PERIPH_RSTEN3_I2C1 0x302 331.1Sjmcneill#define PERIPH_RSTEN3_I2C2 0x303 341.1Sjmcneill#define PERIPH_RSTEN3_I2C3 0x304 351.1Sjmcneill#define PERIPH_RSTEN3_UART1 0x305 361.1Sjmcneill#define PERIPH_RSTEN3_UART2 0x306 371.1Sjmcneill#define PERIPH_RSTEN3_UART3 0x307 381.1Sjmcneill#define PERIPH_RSTEN3_UART4 0x308 391.1Sjmcneill#define PERIPH_RSTEN3_SSP 0x309 401.1Sjmcneill#define PERIPH_RSTEN3_PWM 0x30a 411.1Sjmcneill#define PERIPH_RSTEN3_BLPWM 0x30b 421.1Sjmcneill#define PERIPH_RSTEN3_TSENSOR 0x30c 431.1Sjmcneill#define PERIPH_RSTEN3_DAPB 0x312 441.1Sjmcneill#define PERIPH_RSTEN3_HKADC 0x313 451.1Sjmcneill#define PERIPH_RSTEN3_CODEC_SSI 0x314 461.1Sjmcneill#define PERIPH_RSTEN3_PMUSSI1 0x316 471.1Sjmcneill#define PERIPH_RSTEN8_RS0 0x400 481.1Sjmcneill#define PERIPH_RSTEN8_RS2 0x401 491.1Sjmcneill#define PERIPH_RSTEN8_RS3 0x402 501.1Sjmcneill#define PERIPH_RSTEN8_MS0 0x403 511.1Sjmcneill#define PERIPH_RSTEN8_MS2 0x405 521.1Sjmcneill#define PERIPH_RSTEN8_XG2RAM0 0x406 531.1Sjmcneill#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 541.1Sjmcneill#define PERIPH_RSTEN8_SRAM 0x408 551.1Sjmcneill#define PERIPH_RSTEN8_HARQ 0x40a 561.1Sjmcneill#define PERIPH_RSTEN8_DDRC 0x40c 571.1Sjmcneill#define PERIPH_RSTEN8_DDRC_APB 0x40d 581.1Sjmcneill#define PERIPH_RSTEN8_DDRPACK_APB 0x40e 591.1Sjmcneill#define PERIPH_RSTEN8_DDRT 0x411 601.1Sjmcneill#define PERIPH_RSDIST9_CARM_DAP 0x500 611.1Sjmcneill#define PERIPH_RSDIST9_CARM_ATB 0x501 621.1Sjmcneill#define PERIPH_RSDIST9_CARM_LBUS 0x502 631.1Sjmcneill#define PERIPH_RSDIST9_CARM_POR 0x503 641.1Sjmcneill#define PERIPH_RSDIST9_CARM_CORE 0x504 651.1Sjmcneill#define PERIPH_RSDIST9_CARM_DBG 0x505 661.1Sjmcneill#define PERIPH_RSDIST9_CARM_L2 0x506 671.1Sjmcneill#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 681.1Sjmcneill#define PERIPH_RSDIST9_CARM_ETM 0x508 691.1Sjmcneill 701.1Sjmcneill#define MEDIA_G3D 0 711.1Sjmcneill#define MEDIA_CODEC_VPU 2 721.1Sjmcneill#define MEDIA_CODEC_JPEG 3 731.1Sjmcneill#define MEDIA_ISP 4 741.1Sjmcneill#define MEDIA_ADE 5 751.1Sjmcneill#define MEDIA_MMU 6 761.1Sjmcneill#define MEDIA_XG2RAM1 7 771.1Sjmcneill 781.1.1.3Sskrll#define AO_G3D 1 791.1.1.3Sskrll#define AO_CODECISP 2 801.1.1.3Sskrll#define AO_MCPU 4 811.1.1.3Sskrll#define AO_BBPHARQMEM 5 821.1.1.3Sskrll#define AO_HIFI 8 831.1.1.3Sskrll#define AO_ACPUSCUL2C 12 841.1.1.3Sskrll 851.1Sjmcneill#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 86