1 1.1 jmcneill /* $NetBSD: hisi,hi6220-resets.h,v 1.1.1.3 2020/01/03 14:33:06 skrll Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 jmcneill /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 jmcneill /** 5 1.1 jmcneill * This header provides index for the reset controller 6 1.1 jmcneill * based on hi6220 SoC. 7 1.1 jmcneill */ 8 1.1 jmcneill #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 9 1.1 jmcneill #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 10 1.1 jmcneill 11 1.1 jmcneill #define PERIPH_RSTDIS0_MMC0 0x000 12 1.1 jmcneill #define PERIPH_RSTDIS0_MMC1 0x001 13 1.1 jmcneill #define PERIPH_RSTDIS0_MMC2 0x002 14 1.1 jmcneill #define PERIPH_RSTDIS0_NANDC 0x003 15 1.1 jmcneill #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 16 1.1 jmcneill #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 17 1.1 jmcneill #define PERIPH_RSTDIS0_USBOTG 0x006 18 1.1 jmcneill #define PERIPH_RSTDIS0_USBOTG_32K 0x007 19 1.1 jmcneill #define PERIPH_RSTDIS1_HIFI 0x100 20 1.1 jmcneill #define PERIPH_RSTDIS1_DIGACODEC 0x105 21 1.1 jmcneill #define PERIPH_RSTEN2_IPF 0x200 22 1.1 jmcneill #define PERIPH_RSTEN2_SOCP 0x201 23 1.1 jmcneill #define PERIPH_RSTEN2_DMAC 0x202 24 1.1 jmcneill #define PERIPH_RSTEN2_SECENG 0x203 25 1.1 jmcneill #define PERIPH_RSTEN2_ABB 0x204 26 1.1 jmcneill #define PERIPH_RSTEN2_HPM0 0x205 27 1.1 jmcneill #define PERIPH_RSTEN2_HPM1 0x206 28 1.1 jmcneill #define PERIPH_RSTEN2_HPM2 0x207 29 1.1 jmcneill #define PERIPH_RSTEN2_HPM3 0x208 30 1.1 jmcneill #define PERIPH_RSTEN3_CSSYS 0x300 31 1.1 jmcneill #define PERIPH_RSTEN3_I2C0 0x301 32 1.1 jmcneill #define PERIPH_RSTEN3_I2C1 0x302 33 1.1 jmcneill #define PERIPH_RSTEN3_I2C2 0x303 34 1.1 jmcneill #define PERIPH_RSTEN3_I2C3 0x304 35 1.1 jmcneill #define PERIPH_RSTEN3_UART1 0x305 36 1.1 jmcneill #define PERIPH_RSTEN3_UART2 0x306 37 1.1 jmcneill #define PERIPH_RSTEN3_UART3 0x307 38 1.1 jmcneill #define PERIPH_RSTEN3_UART4 0x308 39 1.1 jmcneill #define PERIPH_RSTEN3_SSP 0x309 40 1.1 jmcneill #define PERIPH_RSTEN3_PWM 0x30a 41 1.1 jmcneill #define PERIPH_RSTEN3_BLPWM 0x30b 42 1.1 jmcneill #define PERIPH_RSTEN3_TSENSOR 0x30c 43 1.1 jmcneill #define PERIPH_RSTEN3_DAPB 0x312 44 1.1 jmcneill #define PERIPH_RSTEN3_HKADC 0x313 45 1.1 jmcneill #define PERIPH_RSTEN3_CODEC_SSI 0x314 46 1.1 jmcneill #define PERIPH_RSTEN3_PMUSSI1 0x316 47 1.1 jmcneill #define PERIPH_RSTEN8_RS0 0x400 48 1.1 jmcneill #define PERIPH_RSTEN8_RS2 0x401 49 1.1 jmcneill #define PERIPH_RSTEN8_RS3 0x402 50 1.1 jmcneill #define PERIPH_RSTEN8_MS0 0x403 51 1.1 jmcneill #define PERIPH_RSTEN8_MS2 0x405 52 1.1 jmcneill #define PERIPH_RSTEN8_XG2RAM0 0x406 53 1.1 jmcneill #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 54 1.1 jmcneill #define PERIPH_RSTEN8_SRAM 0x408 55 1.1 jmcneill #define PERIPH_RSTEN8_HARQ 0x40a 56 1.1 jmcneill #define PERIPH_RSTEN8_DDRC 0x40c 57 1.1 jmcneill #define PERIPH_RSTEN8_DDRC_APB 0x40d 58 1.1 jmcneill #define PERIPH_RSTEN8_DDRPACK_APB 0x40e 59 1.1 jmcneill #define PERIPH_RSTEN8_DDRT 0x411 60 1.1 jmcneill #define PERIPH_RSDIST9_CARM_DAP 0x500 61 1.1 jmcneill #define PERIPH_RSDIST9_CARM_ATB 0x501 62 1.1 jmcneill #define PERIPH_RSDIST9_CARM_LBUS 0x502 63 1.1 jmcneill #define PERIPH_RSDIST9_CARM_POR 0x503 64 1.1 jmcneill #define PERIPH_RSDIST9_CARM_CORE 0x504 65 1.1 jmcneill #define PERIPH_RSDIST9_CARM_DBG 0x505 66 1.1 jmcneill #define PERIPH_RSDIST9_CARM_L2 0x506 67 1.1 jmcneill #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 68 1.1 jmcneill #define PERIPH_RSDIST9_CARM_ETM 0x508 69 1.1 jmcneill 70 1.1 jmcneill #define MEDIA_G3D 0 71 1.1 jmcneill #define MEDIA_CODEC_VPU 2 72 1.1 jmcneill #define MEDIA_CODEC_JPEG 3 73 1.1 jmcneill #define MEDIA_ISP 4 74 1.1 jmcneill #define MEDIA_ADE 5 75 1.1 jmcneill #define MEDIA_MMU 6 76 1.1 jmcneill #define MEDIA_XG2RAM1 7 77 1.1 jmcneill 78 1.1.1.3 skrll #define AO_G3D 1 79 1.1.1.3 skrll #define AO_CODECISP 2 80 1.1.1.3 skrll #define AO_MCPU 4 81 1.1.1.3 skrll #define AO_BBPHARQMEM 5 82 1.1.1.3 skrll #define AO_HIFI 8 83 1.1.1.3 skrll #define AO_ACPUSCUL2C 12 84 1.1.1.3 skrll 85 1.1 jmcneill #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 86
Indexes created Fri Oct 03 02:09:57 GMT 2025