11.1Sjmcneill/* $NetBSD: mt8135-resets.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 21.1Sjmcneill 31.1.1.2Sskrll/* SPDX-License-Identifier: GPL-2.0-only */ 41.1Sjmcneill/* 51.1Sjmcneill * Copyright (c) 2014 MediaTek Inc. 61.1Sjmcneill * Author: Flora Fu, MediaTek 71.1Sjmcneill */ 81.1Sjmcneill 91.1Sjmcneill#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 101.1Sjmcneill#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 111.1Sjmcneill 121.1Sjmcneill/* INFRACFG resets */ 131.1Sjmcneill#define MT8135_INFRA_EMI_REG_RST 0 141.1Sjmcneill#define MT8135_INFRA_DRAMC0_A0_RST 1 151.1Sjmcneill#define MT8135_INFRA_CCIF0_RST 2 161.1Sjmcneill#define MT8135_INFRA_APCIRQ_EINT_RST 3 171.1Sjmcneill#define MT8135_INFRA_APXGPT_RST 4 181.1Sjmcneill#define MT8135_INFRA_SCPSYS_RST 5 191.1Sjmcneill#define MT8135_INFRA_CCIF1_RST 6 201.1Sjmcneill#define MT8135_INFRA_PMIC_WRAP_RST 7 211.1Sjmcneill#define MT8135_INFRA_KP_RST 8 221.1Sjmcneill#define MT8135_INFRA_EMI_RST 32 231.1Sjmcneill#define MT8135_INFRA_DRAMC0_RST 34 241.1Sjmcneill#define MT8135_INFRA_SMI_RST 35 251.1Sjmcneill#define MT8135_INFRA_M4U_RST 36 261.1Sjmcneill 271.1Sjmcneill/* PERICFG resets */ 281.1Sjmcneill#define MT8135_PERI_UART0_SW_RST 0 291.1Sjmcneill#define MT8135_PERI_UART1_SW_RST 1 301.1Sjmcneill#define MT8135_PERI_UART2_SW_RST 2 311.1Sjmcneill#define MT8135_PERI_UART3_SW_RST 3 321.1Sjmcneill#define MT8135_PERI_IRDA_SW_RST 4 331.1Sjmcneill#define MT8135_PERI_PTP_SW_RST 5 341.1Sjmcneill#define MT8135_PERI_AP_HIF_SW_RST 6 351.1Sjmcneill#define MT8135_PERI_GPCU_SW_RST 7 361.1Sjmcneill#define MT8135_PERI_MD_HIF_SW_RST 8 371.1Sjmcneill#define MT8135_PERI_NLI_SW_RST 9 381.1Sjmcneill#define MT8135_PERI_AUXADC_SW_RST 10 391.1Sjmcneill#define MT8135_PERI_DMA_SW_RST 11 401.1Sjmcneill#define MT8135_PERI_NFI_SW_RST 14 411.1Sjmcneill#define MT8135_PERI_PWM_SW_RST 15 421.1Sjmcneill#define MT8135_PERI_THERM_SW_RST 16 431.1Sjmcneill#define MT8135_PERI_MSDC0_SW_RST 17 441.1Sjmcneill#define MT8135_PERI_MSDC1_SW_RST 18 451.1Sjmcneill#define MT8135_PERI_MSDC2_SW_RST 19 461.1Sjmcneill#define MT8135_PERI_MSDC3_SW_RST 20 471.1Sjmcneill#define MT8135_PERI_I2C0_SW_RST 22 481.1Sjmcneill#define MT8135_PERI_I2C1_SW_RST 23 491.1Sjmcneill#define MT8135_PERI_I2C2_SW_RST 24 501.1Sjmcneill#define MT8135_PERI_I2C3_SW_RST 25 511.1Sjmcneill#define MT8135_PERI_I2C4_SW_RST 26 521.1Sjmcneill#define MT8135_PERI_I2C5_SW_RST 27 531.1Sjmcneill#define MT8135_PERI_I2C6_SW_RST 28 541.1Sjmcneill#define MT8135_PERI_USB_SW_RST 29 551.1Sjmcneill#define MT8135_PERI_SPI1_SW_RST 33 561.1Sjmcneill#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 571.1Sjmcneill 581.1Sjmcneill#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ 59