mt8135-resets.h revision 1.1.1.1 
1/*	$NetBSD: mt8135-resets.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2014 MediaTek Inc.
5 * Author: Flora Fu, MediaTek
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
18#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
19
20/* INFRACFG resets */
21#define MT8135_INFRA_EMI_REG_RST        0
22#define MT8135_INFRA_DRAMC0_A0_RST      1
23#define MT8135_INFRA_CCIF0_RST          2
24#define MT8135_INFRA_APCIRQ_EINT_RST    3
25#define MT8135_INFRA_APXGPT_RST         4
26#define MT8135_INFRA_SCPSYS_RST         5
27#define MT8135_INFRA_CCIF1_RST          6
28#define MT8135_INFRA_PMIC_WRAP_RST      7
29#define MT8135_INFRA_KP_RST             8
30#define MT8135_INFRA_EMI_RST            32
31#define MT8135_INFRA_DRAMC0_RST         34
32#define MT8135_INFRA_SMI_RST            35
33#define MT8135_INFRA_M4U_RST            36
34
35/*  PERICFG resets */
36#define MT8135_PERI_UART0_SW_RST        0
37#define MT8135_PERI_UART1_SW_RST        1
38#define MT8135_PERI_UART2_SW_RST        2
39#define MT8135_PERI_UART3_SW_RST        3
40#define MT8135_PERI_IRDA_SW_RST         4
41#define MT8135_PERI_PTP_SW_RST          5
42#define MT8135_PERI_AP_HIF_SW_RST       6
43#define MT8135_PERI_GPCU_SW_RST         7
44#define MT8135_PERI_MD_HIF_SW_RST       8
45#define MT8135_PERI_NLI_SW_RST          9
46#define MT8135_PERI_AUXADC_SW_RST       10
47#define MT8135_PERI_DMA_SW_RST          11
48#define MT8135_PERI_NFI_SW_RST          14
49#define MT8135_PERI_PWM_SW_RST          15
50#define MT8135_PERI_THERM_SW_RST        16
51#define MT8135_PERI_MSDC0_SW_RST        17
52#define MT8135_PERI_MSDC1_SW_RST        18
53#define MT8135_PERI_MSDC2_SW_RST        19
54#define MT8135_PERI_MSDC3_SW_RST        20
55#define MT8135_PERI_I2C0_SW_RST         22
56#define MT8135_PERI_I2C1_SW_RST         23
57#define MT8135_PERI_I2C2_SW_RST         24
58#define MT8135_PERI_I2C3_SW_RST         25
59#define MT8135_PERI_I2C4_SW_RST         26
60#define MT8135_PERI_I2C5_SW_RST         27
61#define MT8135_PERI_I2C6_SW_RST         28
62#define MT8135_PERI_USB_SW_RST          29
63#define MT8135_PERI_SPI1_SW_RST         33
64#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
65
66#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
67