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mt8173-resets.h revision 1.1.1.1 
      1 /*	$NetBSD: mt8173-resets.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2014 MediaTek Inc.
      5  * Author: Flora Fu, MediaTek
      6  *
      7  * This program is free software; you can redistribute it and/or modify
      8  * it under the terms of the GNU General Public License version 2 as
      9  * published by the Free Software Foundation.
     10  *
     11  * This program is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14  * GNU General Public License for more details.
     15  */
     16 
     17 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
     18 #define _DT_BINDINGS_RESET_CONTROLLER_MT8173
     19 
     20 /* INFRACFG resets */
     21 #define MT8173_INFRA_EMI_REG_RST        0
     22 #define MT8173_INFRA_DRAMC0_A0_RST      1
     23 #define MT8173_INFRA_APCIRQ_EINT_RST    3
     24 #define MT8173_INFRA_APXGPT_RST         4
     25 #define MT8173_INFRA_SCPSYS_RST         5
     26 #define MT8173_INFRA_KP_RST             6
     27 #define MT8173_INFRA_PMIC_WRAP_RST      7
     28 #define MT8173_INFRA_MPIP_RST           8
     29 #define MT8173_INFRA_CEC_RST            9
     30 #define MT8173_INFRA_EMI_RST            32
     31 #define MT8173_INFRA_DRAMC0_RST         34
     32 #define MT8173_INFRA_APMIXEDSYS_RST     35
     33 #define MT8173_INFRA_MIPI_DSI_RST       36
     34 #define MT8173_INFRA_TRNG_RST           37
     35 #define MT8173_INFRA_SYSIRQ_RST         38
     36 #define MT8173_INFRA_MIPI_CSI_RST       39
     37 #define MT8173_INFRA_GCE_FAXI_RST       40
     38 #define MT8173_INFRA_MMIOMMURST         47
     39 
     40 
     41 /*  PERICFG resets */
     42 #define MT8173_PERI_UART0_SW_RST        0
     43 #define MT8173_PERI_UART1_SW_RST        1
     44 #define MT8173_PERI_UART2_SW_RST        2
     45 #define MT8173_PERI_UART3_SW_RST        3
     46 #define MT8173_PERI_IRRX_SW_RST         4
     47 #define MT8173_PERI_PWM_SW_RST          8
     48 #define MT8173_PERI_AUXADC_SW_RST       10
     49 #define MT8173_PERI_DMA_SW_RST          11
     50 #define MT8173_PERI_I2C6_SW_RST         13
     51 #define MT8173_PERI_NFI_SW_RST          14
     52 #define MT8173_PERI_THERM_SW_RST        16
     53 #define MT8173_PERI_MSDC2_SW_RST        17
     54 #define MT8173_PERI_MSDC3_SW_RST        18
     55 #define MT8173_PERI_MSDC0_SW_RST        19
     56 #define MT8173_PERI_MSDC1_SW_RST        20
     57 #define MT8173_PERI_I2C0_SW_RST         22
     58 #define MT8173_PERI_I2C1_SW_RST         23
     59 #define MT8173_PERI_I2C2_SW_RST         24
     60 #define MT8173_PERI_I2C3_SW_RST         25
     61 #define MT8173_PERI_I2C4_SW_RST         26
     62 #define MT8173_PERI_HDMI_SW_RST         29
     63 #define MT8173_PERI_SPI0_SW_RST         33
     64 
     65 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */
     66