11.1Sskrll/* $NetBSD: mt8186-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2022 MediaTek Inc. 61.1Sskrll * Author: Runyang Chen <runyang.chen@mediatek.com> 71.1Sskrll */ 81.1Sskrll 91.1Sskrll#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 101.1Sskrll#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 111.1Sskrll 121.1Sskrll/* TOPRGU resets */ 131.1Sskrll#define MT8186_TOPRGU_INFRA_SW_RST 0 141.1Sskrll#define MT8186_TOPRGU_MM_SW_RST 1 151.1Sskrll#define MT8186_TOPRGU_MFG_SW_RST 2 161.1Sskrll#define MT8186_TOPRGU_VENC_SW_RST 3 171.1Sskrll#define MT8186_TOPRGU_VDEC_SW_RST 4 181.1Sskrll#define MT8186_TOPRGU_IMG_SW_RST 5 191.1Sskrll#define MT8186_TOPRGU_DDR_SW_RST 6 201.1Sskrll#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 211.1Sskrll#define MT8186_TOPRGU_CONNSYS_SW_RST 9 221.1Sskrll#define MT8186_TOPRGU_APMIXED_SW_RST 10 231.1Sskrll#define MT8186_TOPRGU_PWRAP_SW_RST 11 241.1Sskrll#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 251.1Sskrll#define MT8186_TOPRGU_IPNNA_SW_RST 13 261.1Sskrll#define MT8186_TOPRGU_WPE_SW_RST 14 271.1Sskrll#define MT8186_TOPRGU_ADSP_SW_RST 15 281.1Sskrll#define MT8186_TOPRGU_AUDIO_SW_RST 17 291.1Sskrll#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 301.1Sskrll#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 311.1Sskrll#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 321.1Sskrll#define MT8186_TOPRGU_IPE_SW_RST 21 331.1Sskrll#define MT8186_TOPRGU_IMG2_SW_RST 22 341.1Sskrll#define MT8186_TOPRGU_SW_RST_NUM 23 351.1Sskrll 361.1Sskrll/* MMSYS resets */ 371.1Sskrll#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 381.1Sskrll 391.1Sskrll/* INFRA resets */ 401.1Sskrll#define MT8186_INFRA_THERMAL_CTRL_RST 0 411.1Sskrll#define MT8186_INFRA_PTP_CTRL_RST 1 421.1Sskrll 431.1Sskrll#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ 44