mt8186-resets.h revision 1.1.1.1
1/* $NetBSD: mt8186-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 4/* 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Runyang Chen <runyang.chen@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 10#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 11 12/* TOPRGU resets */ 13#define MT8186_TOPRGU_INFRA_SW_RST 0 14#define MT8186_TOPRGU_MM_SW_RST 1 15#define MT8186_TOPRGU_MFG_SW_RST 2 16#define MT8186_TOPRGU_VENC_SW_RST 3 17#define MT8186_TOPRGU_VDEC_SW_RST 4 18#define MT8186_TOPRGU_IMG_SW_RST 5 19#define MT8186_TOPRGU_DDR_SW_RST 6 20#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 21#define MT8186_TOPRGU_CONNSYS_SW_RST 9 22#define MT8186_TOPRGU_APMIXED_SW_RST 10 23#define MT8186_TOPRGU_PWRAP_SW_RST 11 24#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 25#define MT8186_TOPRGU_IPNNA_SW_RST 13 26#define MT8186_TOPRGU_WPE_SW_RST 14 27#define MT8186_TOPRGU_ADSP_SW_RST 15 28#define MT8186_TOPRGU_AUDIO_SW_RST 17 29#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 30#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 31#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 32#define MT8186_TOPRGU_IPE_SW_RST 21 33#define MT8186_TOPRGU_IMG2_SW_RST 22 34#define MT8186_TOPRGU_SW_RST_NUM 23 35 36/* MMSYS resets */ 37#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 38 39/* INFRA resets */ 40#define MT8186_INFRA_THERMAL_CTRL_RST 0 41#define MT8186_INFRA_PTP_CTRL_RST 1 42 43#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ 44