11.1Sskrll/* $NetBSD: mt8192-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 21.1Sskrll 31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 */ 41.1Sskrll/* 51.1Sskrll * Copyright (c) 2020 MediaTek Inc. 61.1Sskrll * Author: Yong Liang <yong.liang@mediatek.com> 71.1Sskrll */ 81.1Sskrll 91.1Sskrll#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 101.1Sskrll#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 111.1Sskrll 121.1Sskrll/* TOPRGU resets */ 131.1Sskrll#define MT8192_TOPRGU_MM_SW_RST 1 141.1Sskrll#define MT8192_TOPRGU_MFG_SW_RST 2 151.1Sskrll#define MT8192_TOPRGU_VENC_SW_RST 3 161.1Sskrll#define MT8192_TOPRGU_VDEC_SW_RST 4 171.1Sskrll#define MT8192_TOPRGU_IMG_SW_RST 5 181.1Sskrll#define MT8192_TOPRGU_MD_SW_RST 7 191.1Sskrll#define MT8192_TOPRGU_CONN_SW_RST 9 201.1Sskrll#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 211.1Sskrll#define MT8192_TOPRGU_IPU0_SW_RST 14 221.1Sskrll#define MT8192_TOPRGU_IPU1_SW_RST 15 231.1Sskrll#define MT8192_TOPRGU_AUDIO_SW_RST 17 241.1Sskrll#define MT8192_TOPRGU_CAMSYS_SW_RST 18 251.1Sskrll#define MT8192_TOPRGU_MJC_SW_RST 19 261.1Sskrll#define MT8192_TOPRGU_C2K_S2_SW_RST 20 271.1Sskrll#define MT8192_TOPRGU_C2K_SW_RST 21 281.1Sskrll#define MT8192_TOPRGU_PERI_SW_RST 22 291.1Sskrll#define MT8192_TOPRGU_PERI_AO_SW_RST 23 301.1Sskrll 311.1Sskrll#define MT8192_TOPRGU_SW_RST_NUM 23 321.1Sskrll 331.1Sskrll/* MMSYS resets */ 341.1Sskrll#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 351.1Sskrll 361.1Sskrll/* INFRA resets */ 371.1Sskrll#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 381.1Sskrll#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 391.1Sskrll#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 401.1Sskrll#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 411.1Sskrll#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 421.1Sskrll 431.1Sskrll#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ 44